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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Cortex-M3 IRQ management.
35 * \author Andrea Righi <arighi@develer.com>
40 #include <cfg/debug.h> /* ASSERT() */
41 #include <cfg/log.h> /* LOG_ERR() */
44 static void (*irq_table[NUM_INTERRUPTS])(void)
45 __attribute__((section("vtable")));
47 /* Priority register / IRQ number table */
48 static const uint32_t nvic_prio_reg[] =
50 /* System exception registers */
51 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3,
53 /* External interrupts registers */
54 NVIC_PRI0, NVIC_PRI1, NVIC_PRI2, NVIC_PRI3,
55 NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
56 NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11,
57 NVIC_PRI12, NVIC_PRI13
61 static NAKED NORETURN void unhandled_isr(void)
63 register uint32_t reg;
65 asm volatile ("mrs %0, ipsr" : "=r"(reg));
66 LOG_ERR("unhandled IRQ %lu\n", reg);
71 void sysirq_setPriority(sysirq_t irq, int prio)
73 uint32_t pos = (irq & 3) * 8;
74 reg32_t reg = nvic_prio_reg[irq >> 2];
78 val &= ~(0xff << pos);
83 static void sysirq_enable(sysirq_t irq)
85 /* Enable the IRQ line (only for generic IRQs) */
86 if (irq >= 16 && irq < 48)
87 NVIC_EN0_R = 1 << (irq - 16);
89 NVIC_EN1_R = 1 << (irq - 48);
92 void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
96 ASSERT(irq < NUM_INTERRUPTS);
98 IRQ_SAVE_DISABLE(flags);
99 irq_table[irq] = handler;
100 sysirq_setPriority(irq, IRQ_PRIO);
105 void sysirq_freeHandler(sysirq_t irq)
109 ASSERT(irq < NUM_INTERRUPTS);
111 IRQ_SAVE_DISABLE(flags);
112 irq_table[irq] = unhandled_isr;
116 void sysirq_init(void)
121 IRQ_SAVE_DISABLE(flags);
122 for (i = 0; i < NUM_INTERRUPTS; i++)
123 irq_table[i] = unhandled_isr;
125 /* Update NVIC to point to the new vector table */
126 NVIC_VTABLE_R = (size_t)irq_table;