4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 debug support (implementation).
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include <cfg/cfg_debug.h>
40 #include <drv/gpio_stm32.h>
41 #include <drv/clock_stm32.h> /* RCC */
43 #include "kdebug_stm32.h"
45 #define CR1_RUN_SET ((uint16_t)0x2000) /* USART Enable MASK */
46 #define CR1_RUN_RESET ((uint16_t)0xDFFF) /* USART Disable MASK */
47 #define CR1_RWU_SET ((uint16_t)0x0002) /* USART mute mode Enable MASK */
48 #define CR1_RWU_RESET ((uint16_t)0xFFFD) /* USART mute mode Enable MASK */
49 #define CR1_SBK_SET ((uint16_t)0x0001) /* USART Break Character send MASK */
50 #define CR1_CLEAR_MASK ((uint16_t)0xE9F3) /* USART CR1 MASK */
52 #define CR2_MASK ((uint16_t)0xFFF0) /* USART address MASK */
53 #define CR2_LINE_SET ((uint16_t)0x4000) /* USART LIN Enable MASK */
54 #define CR2_LINE_RESET ((uint16_t)0xBFFF) /* USART LIN Disable MASK */
55 #define CR2_CLEAR_MASK ((uint16_t)0xC0FF) /* USART CR2 MASK */
57 #define CR3_SCEN_SET ((uint16_t)0x0020) /* USART SC Enable MASK */
58 #define CR3_SCEN_RESET ((uint16_t)0xFFDF) /* USART SC Disable MASK */
59 #define CR3_NACK_SET ((uint16_t)0x0010) /* USART SC NACK Enable MASK */
60 #define CR3_NACK_RESET ((uint16_t)0xFFEF) /* USART SC NACK Disable MASK */
61 #define CR3_HDSEL_SET ((uint16_t)0x0008) /* USART Half-Duplex Enable MASK */
62 #define CR3_HDSEL_RESET ((uint16_t)0xFFF7) /* USART Half-Duplex Disable MASK */
63 #define CR3_IRLP_MASK ((uint16_t)0xFFFB) /* USART IrDA LowPower mode MASK */
64 #define CR3_LBDL_MASK ((uint16_t)0xFFDF) /* USART LIN Break detection MASK */
65 #define CR3_WAKE_MASK ((uint16_t)0xF7FF) /* USART WakeUp Method MASK */
66 #define CR3_IREN_SET ((uint16_t)0x0002) /* USART IrDA Enable MASK */
67 #define CR3_IREN_RESET ((uint16_t)0xFFFD) /* USART IrDA Disable MASK */
68 #define CR3_CLEAR_MASK ((uint16_t)0xFCFF) /* USART CR3 MASK */
70 #define GTPR_LSB_MASK ((uint16_t)0x00FF) /* Guard Time Register LSB MASK */
71 #define GTPR_MSB_MASK ((uint16_t)0xFF00) /* Guard Time Register MSB MASK */
73 #define USART_IT_MASK ((uint16_t)0x001F) /* USART Interrupt MASK */
76 #define USART_FLAG_CTS ((uint16_t)0x0200)
77 #define USART_FLAG_LBD ((uint16_t)0x0100)
78 #define USART_FLAG_TXE ((uint16_t)0x0080)
79 #define USART_FLAG_TC ((uint16_t)0x0040)
80 #define USART_FLAG_RXNE ((uint16_t)0x0020)
81 #define USART_FLAG_IDLE ((uint16_t)0x0010)
82 #define USART_FLAG_ORE ((uint16_t)0x0008)
83 #define USART_FLAG_NE ((uint16_t)0x0004)
84 #define USART_FLAG_FE ((uint16_t)0x0002)
85 #define USART_FLAG_PE ((uint16_t)0x0001)
107 #define USART_MODE_RX ((uint16_t)0x0004)
108 #define USART_MODE_TX ((uint16_t)0x0008)
111 #define USART_LASTBIT_DISABLE ((uint16_t)0x0000)
112 #define USART_LASTBIT_ENABLE ((uint16_t)0x0100)
114 #if CONFIG_KDEBUG_PORT == 0
115 #define UART_BASE ((struct stm32_usart *)USART1_BASE)
116 #elif CONFIG_KDEBUG_PORT == 1
117 #define UART_BASE ((struct stm32_usart *)USART2_BASE)
118 #elif CONFIG_KDEBUG_PORT == 2
119 #define UART_BASE ((struct stm32_usart *)USART3_BASE)
121 #error "UART port not supported in this board"
124 #define KDBG_WAIT_READY() while (!(UART_BASE->SR & USART_FLAG_TXE))
125 #define KDBG_WAIT_TXDONE() while (!(UART_BASE->SR & USART_FLAG_TC))
127 #define KDBG_WRITE_CHAR(c) do { UART_BASE->DR = (c) & 0x1ff; } while(0)
129 /* Debug unit is used only for debug purposes so does not generate interrupts. */
130 #define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
132 /* Debug unit is used only for debug purposes so does not generate interrupts. */
133 #define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
135 typedef uint32_t kdbg_irqsave_t;
137 #define GPIO_USART1_TX_PIN (1 << 9)
138 #define GPIO_USART1_RX_PIN (1 << 10)
140 #define GPIO_USART2_TX_PIN (1 << 2)
141 #define GPIO_USART2_RX_PIN (1 << 3)
143 #define GPIO_USART3_TX_PIN (1 << 13)
144 #define GPIO_USART3_RX_PIN (1 << 14)
146 INLINE uint16_t evaluate_brr(void)
148 uint32_t freq, reg, div, frac;
150 /* NOTE: PCLK1 has been configured as CPU_FREQ / 2 */
151 freq = (CONFIG_KDEBUG_PORT == 0) ? CPU_FREQ : CPU_FREQ / 2;
152 div = (0x19 * freq) / (0x04 * CONFIG_KDEBUG_BAUDRATE);
153 reg = (div / 0x64) << 0x04;
154 frac = div - (0x64 * (reg >> 0x04));
155 reg |= ((frac * 0x10 + 0x32) / 0x64) & 0x0f;
157 return (uint16_t)reg;
160 /* Initialize UART debug port */
161 INLINE void kdbg_hw_init(void)
163 /* Enable clocking on AFIO */
164 RCC->APB2ENR |= RCC_APB2_AFIO;
165 /* Configure USART pins */
166 #if CONFIG_KDEBUG_PORT == 0
167 RCC->APB2ENR |= RCC_APB2_GPIOA;
168 RCC->APB2ENR |= RCC_APB2_USART1;
169 stm32_gpioPinConfig((struct stm32_gpio *)GPIOA_BASE, GPIO_USART1_TX_PIN,
170 GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
171 #elif CONFIG_KDEBUG_PORT == 1
172 RCC->APB2ENR |= RCC_APB2_GPIOA;
173 RCC->APB1ENR |= RCC_APB1_USART2;
174 stm32_gpioPinConfig((struct stm32_gpio *)GPIOA_BASE, GPIO_USART2_TX_PIN,
175 GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
176 #elif CONFIG_KDEBUG_PORT == 2
177 RCC->APB2ENR |= RCC_APB2_GPIOB;
178 RCC->APB2ENR |= RCC_APB1_USART3;
179 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_USART3_TX_PIN,
180 GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
182 #error "UART port not supported in this board"
184 /* Enable the USART by writing the UE bit */
185 UART_BASE->CR1 |= CR1_RUN_SET;
186 /* Configure the desired baud rate */
187 UART_BASE->BRR = evaluate_brr();
188 /* Set the Transmitter Enable bit in CR1 */
189 UART_BASE->CR1 |= USART_MODE_TX;