4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
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9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
38 * \author Daniele Basile <asterix@develer.com>
43 #include <hw/hw_cpu.h>
45 #include <cfg/macros.h>
46 #include <cfg/debug.h>
49 #include "appconfig.h"
52 * Register structure for pwm driver.
53 * This array content all data and register pointer
54 * to manage pwm peripheral device.
56 static PwmChannel pwm_map[PWM_CNT] =
61 .mode_reg = &PWM_CMR0,
62 .duty_reg = &PWM_CDTY0,
63 .period_reg = &PWM_CPRD0,
64 .update_reg = &PWM_CUPD0,
69 .mode_reg = &PWM_CMR1,
70 .duty_reg = &PWM_CDTY1,
71 .period_reg = &PWM_CPRD1,
72 .update_reg = &PWM_CUPD1,
77 .mode_reg = &PWM_CMR2,
78 .duty_reg = &PWM_CDTY2,
79 .period_reg = &PWM_CPRD2,
80 .update_reg = &PWM_CUPD2,
85 .mode_reg = &PWM_CMR3,
86 .duty_reg = &PWM_CDTY3,
87 .period_reg = &PWM_CPRD3,
88 .update_reg = &PWM_CUPD3,
94 * Get preiod from select channel
98 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
100 return *pwm_map[dev].period_reg;
104 * Set pwm waveform frequecy.
108 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
112 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
114 period = CLOCK_FREQ / (BV(i) * freq);
115 // TRACEMSG("period[%d], prescale[%d]", period, i);
116 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
118 //Clean previous channel prescaler, and set new
119 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
120 *pwm_map[dev].mode_reg |= i;
122 *pwm_map[dev].period_reg = period;
129 // TRACEMSG("PWM ch[%d] period[%d]", dev, period);
133 * Set pwm duty cycle.
135 * \a duty value 0 - 2^16
137 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
139 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
143 * WARNING: is forbidden to write 0 to duty cycle value,
144 * and so for duty = 0 we must enable PIO and clear output!
148 PWM_PIO_PER = pwm_map[dev].pwm_pin;
149 pwm_map[dev].duty_zero = true;
154 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
155 *pwm_map[dev].update_reg = duty;
156 pwm_map[dev].duty_zero = false;
159 // TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
164 * Enable select pwm channel
166 void pwm_hw_enable(PwmDev dev)
168 if (!pwm_map[dev].duty_zero)
169 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
173 * Disable select pwm channel
175 void pwm_hw_disable(PwmDev dev)
177 PWM_PIO_PER = pwm_map[dev].pwm_pin;
184 void pwm_hw_init(void)
189 * WARNING: is forbidden to write 0 to duty cycle value,
190 * and so for duty = 0 we must enable PIO and clear output!
191 * - clear PIO outputs
192 * - enable PIO outputs
193 * - Disable PIO and enable PWM functions
196 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
197 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
198 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
199 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
200 PMC_PCER |= BV(PWMC_ID);
202 /* Disable all channels. */
203 PWM_DIS = 0xFFFFFFFF;
204 /* Disable prescalers A and B */
209 * - set period alidned to left
210 * - set output waveform to low level
211 * - allow duty cycle modify at next period event
213 for (int ch = 0; ch < PWM_CNT; ch++)
214 *pwm_map[ch].mode_reg = 0;