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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 RTC driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include "clock_stm32.h"
40 #include <cfg/compiler.h>
41 #include <cfg/debug.h>
44 #include <io/stm32_pwr.h>
46 #include <cpu/power.h> // cpu_relax()
50 /* PWR registers base */
51 static struct PWR *PWR = (struct PWR *)PWR_BASE;
53 /* RTC clock source: LSE */
54 #define RTC_CLKSRC 0x00000100
55 /* RTC clock: 32768 Hz */
56 #define RTC_CLOCK 32768
57 /* RTC clock period (in ms) */
58 #define RTC_PERIOD 1000
60 /* RTC control register */
61 #define RTC_CRH (*(reg16_t *)(RTC_BASE + 0x00))
62 #define RTC_CRL (*(reg16_t *)(RTC_BASE + 0x04))
64 #define RTC_CRL_SECIE BV(0)
65 #define RTC_CRL_ALRIE BV(1)
66 #define RTC_CRL_OWIE BV(2)
68 #define RTC_CRL_SECF BV(0)
69 #define RTC_CRL_ALRF BV(1)
70 #define RTC_CRL_OWF BV(2)
71 #define RTC_CRL_RSF BV(3)
72 #define RTC_CRL_CNF BV(4)
73 #define RTC_CRL_RTOFF BV(5)
75 /* RTC prescaler load register */
76 #define RTC_PRLH (*(reg16_t *)(RTC_BASE + 0x08))
77 #define RTC_PRLL (*(reg16_t *)(RTC_BASE + 0x0c))
79 /* RTC prescaler divider register */
80 #define RTC_DIVH (*(reg16_t *)(RTC_BASE + 0x10))
81 #define RTC_DIVL (*(reg16_t *)(RTC_BASE + 0x14))
83 /* RTC counter register */
84 #define RTC_CNTH (*(reg16_t *)(RTC_BASE + 0x18))
85 #define RTC_CNTL (*(reg16_t *)(RTC_BASE + 0x1c))
87 /* RTC alarm register */
88 #define RTC_ALRH (*(reg16_t *)(RTC_BASE + 0x20))
89 #define RTC_ALRL (*(reg16_t *)(RTC_BASE + 0x24))
91 static void rtc_enterConfig(void)
93 /* Enter configuration mode */
94 RTC_CRL |= RTC_CRL_CNF;
97 static void rtc_exitConfig(void)
99 /* Exit from configuration mode */
100 RTC_CRL &= ~RTC_CRL_CNF;
101 while (!(RTC_CRL & RTC_CRL_RTOFF))
105 uint32_t rtc_time(void)
107 return (RTC_CNTH << 16) | RTC_CNTL;
110 void rtc_setTime(uint32_t val)
113 RTC_CNTH = (val >> 16) & 0xffff;
114 RTC_CNTL = val & 0xffff;
118 /* Initialize the RTC clock */
124 /* Enable clock for Power interface */
125 RCC->APB1ENR |= RCC_APB1_PWR;
127 /* Enable access to RTC registers */
128 PWR->CR |= PWR_CR_DBP;
131 RCC->BDCR |= RCC_BDCR_LSEON;
132 /* Wait for LSE ready */
133 while (!(RCC->BDCR & RCC_BDCR_LSERDY))
136 /* Set clock source and enable RTC peripheral */
137 RCC->BDCR |= RTC_CLKSRC | RCC_BDCR_RTCEN;
142 RTC_PRLH = ((RTC_PERIOD * RTC_CLOCK / 1000 - 1) >> 16) & 0xff;
143 RTC_PRLL = ((RTC_PERIOD * RTC_CLOCK / 1000 - 1)) & 0xffff;
147 /* Disable access to the RTC registers */
148 PWR->CR &= ~PWR_CR_DBP;