4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.11 2004/08/25 14:12:08 rasky
42 *#* Aggiornato il comment block dei log RCS
44 *#* Revision 1.10 2004/08/10 06:30:41 bernie
45 *#* Major redesign of serial bus policy handling.
47 *#* Revision 1.9 2004/08/02 20:20:29 aleph
48 *#* Merge from project_ks
50 *#* Revision 1.8 2004/07/29 22:57:09 bernie
51 *#* Several tweaks to reduce code size on ATmega8.
53 *#* Revision 1.7 2004/07/18 21:54:23 bernie
54 *#* Add ATmega8 support.
56 *#* Revision 1.5 2004/06/27 15:25:40 aleph
57 *#* Add missing callbacks for SPI;
58 *#* Change UNUSED() macro to new version with two args;
59 *#* Use TX line filling only on the correct KBUS serial port;
60 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
62 *#* Revision 1.4 2004/06/03 11:27:09 bernie
63 *#* Add dual-license information.
65 *#* Revision 1.3 2004/06/02 21:35:24 aleph
66 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
68 *#* Revision 1.2 2004/05/23 18:21:53 bernie
69 *#* Trim CVS logs and cleanup header info.
78 #include <drv/timer.h>
79 #include <mware/fifobuf.h>
81 #include <avr/signal.h>
85 * \name Hardware handshake (RTS/CTS).
89 #define RTS_ON do {} while (0)
92 #define RTS_OFF do {} while (0)
95 #define IS_CTS_ON true
98 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
104 * \def CONFIG_SER_STROBE
106 * This is a debug facility that can be used to
107 * monitor SER interrupt activity on an external pin.
109 * To use strobes, redefine the macros SER_STROBE_ON,
110 * SER_STROBE_OFF and SER_STROBE_INIT and set
111 * CONFIG_SER_STROBE to 1.
113 #ifndef CONFIG_SER_STROBE
114 #define SER_STROBE_ON do {/*nop*/} while(0)
115 #define SER_STROBE_OFF do {/*nop*/} while(0)
116 #define SER_STROBE_INIT do {/*nop*/} while(0)
121 * \name Overridable serial hooks
123 * These can be redefined in hw.h to implement
124 * special bus policies such as half-duplex, 485, etc.
128 * TXBEGIN TXCHAR TXEND TXOFF
129 * | __________|__________ | |
132 * ______ __ __ __ __ __ __ ________________
133 * \/ \/ \/ \/ \/ \/ \/
134 * ______/\__/\__/\__/\__/\__/\__/
140 #ifndef SER_UART0_BUS_TXINIT
142 * Default TXINIT macro - invoked in uart0_init()
144 * - Enable both the receiver and the transmitter
145 * - Enable only the RX complete interrupt
147 #define SER_UART0_BUS_TXINIT do { \
148 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
152 #ifndef SER_UART0_BUS_TXBEGIN
154 * Invoked before starting a transmission
156 * - Enable both the receiver and the transmitter
157 * - Enable both the RX complete and UDR empty interrupts
159 #define SER_UART0_BUS_TXBEGIN do { \
160 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
164 #ifndef SER_UART0_BUS_TXCHAR
166 * Invoked to send one character.
168 #define SER_UART0_BUS_TXCHAR(c) do { \
173 #ifndef SER_UART0_BUS_TXEND
175 * Invoked as soon as the txfifo becomes empty
177 * - Keep both the receiver and the transmitter enabled
178 * - Keep the RX complete interrupt enabled
179 * - Disable the UDR empty interrupt
181 #define SER_UART0_BUS_TXEND do { \
182 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
186 #ifndef SER_UART0_BUS_TXOFF
188 * \def SER_UART0_BUS_TXOFF
190 * Invoked after the last character has been transmitted
192 * The default is no action.
196 #ifndef SER_UART1_BUS_TXINIT
197 /*! \sa SER_UART0_BUS_TXINIT */
198 #define SER_UART1_BUS_TXINIT do { \
199 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
202 #ifndef SER_UART1_BUS_TXBEGIN
203 /*! \sa SER_UART0_BUS_TXBEGIN */
204 #define SER_UART1_BUS_TXBEGIN do { \
205 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
208 #ifndef SER_UART1_BUS_TXCHAR
209 /*! \sa SER_UART0_BUS_TXCHAR */
210 #define SER_UART1_BUS_TXCHAR(c) do { \
214 #ifndef SER_UART1_BUS_TXEND
215 /*! \sa SER_UART0_BUS_TXEND */
216 #define SER_UART1_BUS_TXEND do { \
217 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
220 #ifndef SER_UART1_BUS_TXOFF
222 * \def SER_UART1_BUS_TXOFF
224 * \see SER_UART0_BUS_TXOFF
230 /* SPI port and pin configuration */
231 #define SPI_PORT PORTB
233 #define SPI_SCK_BIT PORTB1
234 #define SPI_MOSI_BIT PORTB2
235 #define SPI_MISO_BIT PORTB3
237 /* USART registers definitions */
238 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
239 #define AVR_HAS_UART1 1
240 #elif defined(__AVR_ATmega8__)
241 #define AVR_HAS_UART1 0
248 #define SIG_UART0_DATA SIG_UART_DATA
249 #define SIG_UART0_RECV SIG_UART_RECV
250 #elif defined(__AVR_ATmega103__)
251 #define AVR_HAS_UART1 0
256 #define SIG_UART0_DATA SIG_UART_DATA
257 #define SIG_UART0_RECV SIG_UART_RECV
259 #error Unknown architecture
263 /* From the high-level serial driver */
264 extern struct Serial ser_handles[SER_CNT];
267 * Internal hardware state structure
269 * \a sending var is true if we are transmitting.
270 * SPI note: this flag is necessary because the SPI sends and receives bytes
271 * at the same time and the SPI IRQ is unique for send/receive.
272 * The only way to start transmission is to write data in SPDR (this
273 * is done by spi_starttx()). We do this *only* if a transfer is
274 * not already started.
276 * For the USARTs the \a sending flag is useful for taking specific
277 * actions before sending a burst of data, at the start of a trasmission
278 * but not before every char sent.
282 struct SerialHardware hw;
283 volatile bool sending;
287 * These are to trick GCC into *not* using
288 * absolute addressing mode when accessing
289 * ser_handles, which is very expensive.
291 * Accessing through these pointers generates
292 * much shorter (and hopefully faster) code.
294 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
296 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
298 struct Serial *ser_spi = &ser_handles[SER_SPI];
305 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
307 SER_UART0_BUS_TXINIT;
311 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
316 static void uart0_enabletxirq(struct SerialHardware *_hw)
318 struct AvrSerial *hw = (struct AvrSerial *)_hw;
321 * WARNING: racy code here! The tx interrupt
322 * sets hw->sending to false when it runs with
323 * an empty fifo. The order of the statements
324 * in the if-block matters.
329 SER_UART0_BUS_TXBEGIN;
333 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
335 /* Compute baud-rate period */
336 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
338 #ifndef __AVR_ATmega103__
339 UBRR0H = (period) >> 8;
343 DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
346 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
348 #ifndef __AVR_ATmega103__
349 UCSR0C |= (parity) << UPM0;
355 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
357 SER_UART1_BUS_TXINIT;
362 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
367 static void uart1_enabletxirq(struct SerialHardware *_hw)
369 struct AvrSerial *hw = (struct AvrSerial *)_hw;
372 * WARNING: racy code here! The tx interrupt
373 * sets hw->sending to false when it runs with
374 * an empty fifo. The order of the statements
375 * in the if-block matters.
380 SER_UART1_BUS_TXBEGIN;
384 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
386 /* Compute baud-rate period */
387 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
389 UBRR1H = (period) >> 8;
392 DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
395 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
397 UCSR1C |= (parity) << UPM0;
400 #endif // AVR_HAS_UART1
402 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
405 * Set MOSI and SCK ports out, MISO in.
407 * The ATmega64/128 datasheet explicitly states that the input/output
408 * state of the SPI pins is not significant, as when the SPI is
409 * active the I/O port are overrided.
410 * This is *blatantly FALSE*.
412 * Moreover, the MISO pin on the board_kc *must* be in high impedance
413 * state even when the SPI is off, because the line is wired together
414 * with the KBus serial RX, and the transmitter of the slave boards
415 * would be unable to drive the line.
417 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
418 SPI_DDR &= ~BV(SPI_MISO_BIT);
419 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
420 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
423 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
426 /* Set all pins as inputs */
427 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
430 static void spi_starttx(struct SerialHardware *_hw)
432 struct AvrSerial *hw = (struct AvrSerial *)_hw;
435 DISABLE_IRQSAVE(flags);
437 /* Send data only if the SPI is not already transmitting */
438 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
441 SPDR = fifo_pop(&ser_spi->txfifo);
444 ENABLE_IRQRESTORE(flags);
447 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
452 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
460 * High-level interface data structures
462 static const struct SerialHardwareVT UART0_VT =
465 .cleanup = uart0_cleanup,
466 .setbaudrate = uart0_setbaudrate,
467 .setparity = uart0_setparity,
468 .enabletxirq = uart0_enabletxirq,
472 static const struct SerialHardwareVT UART1_VT =
475 .cleanup = uart1_cleanup,
476 .setbaudrate = uart1_setbaudrate,
477 .setparity = uart1_setparity,
478 .enabletxirq = uart1_enabletxirq,
480 #endif // AVR_HAS_UART1
482 static const struct SerialHardwareVT SPI_VT =
485 .cleanup = spi_cleanup,
486 .setbaudrate = spi_setbaudrate,
487 .setparity = spi_setparity,
488 .enabletxirq = spi_starttx,
491 static struct AvrSerial UARTDescs[SER_CNT] =
494 .hw = { .table = &UART0_VT },
499 .hw = { .table = &UART1_VT },
504 .hw = { .table = &SPI_VT },
509 struct SerialHardware* ser_hw_getdesc(int unit)
511 ASSERT(unit < SER_CNT);
512 return &UARTDescs[unit].hw;
521 #if CONFIG_SER_HWHANDSHAKE
523 //! This interrupt is triggered when the CTS line goes high
526 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
527 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
528 cbi(EIMSK, EIMSKB_CTS);
531 #endif // CONFIG_SER_HWHANDSHAKE
535 * Serial 0 TX interrupt handler
537 SIGNAL(SIG_UART0_DATA)
541 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
543 if (fifo_isempty(txfifo))
546 #ifndef SER_UART0_BUS_TXOFF
547 UARTDescs[SER_UART0].sending = false;
550 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
553 // Disable rx interrupt and tx, enable CTS interrupt
555 UCSR0B = BV(RXCIE) | BV(RXEN);
556 sbi(EIFR, EIMSKB_CTS);
557 sbi(EIMSK, EIMSKB_CTS);
562 char c = fifo_pop(txfifo);
563 SER_UART0_BUS_TXCHAR(c);
569 #ifdef SER_UART0_BUS_TXOFF
571 * Serial port 0 TX complete interrupt handler.
573 * This IRQ is usually disabled. The UDR-empty interrupt
574 * enables it when there's no more data to transmit.
575 * We need to wait until the last character has been
576 * transmitted before switching the 485 transceiver to
579 * The txfifo might have been refilled by putchar() while
580 * we were waiting for the transmission complete interrupt.
581 * In this case, we must restart the UDR empty interrupt,
582 * otherwise we'd stop the serial port with some data
583 * still pending in the buffer.
585 SIGNAL(SIG_UART0_TRANS)
589 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
590 if (fifo_isempty(txfifo))
593 UARTDescs[SER_UART0].sending = false;
596 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
600 #endif /* SER_UART0_BUS_TXOFF */
606 * Serial 1 TX interrupt handler
608 SIGNAL(SIG_UART1_DATA)
612 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
614 if (fifo_isempty(txfifo))
617 #ifndef SER_UART1_BUS_TXOFF
618 UARTDescs[SER_UART1].sending = false;
621 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
624 // Disable rx interrupt and tx, enable CTS interrupt
626 UCSR1B = BV(RXCIE) | BV(RXEN);
627 sbi(EIFR, EIMSKB_CTS);
628 sbi(EIMSK, EIMSKB_CTS);
633 char c = fifo_pop(txfifo);
634 SER_UART1_BUS_TXCHAR(c);
640 #ifdef SER_UART1_BUS_TXOFF
642 * Serial port 1 TX complete interrupt handler.
644 * \sa port 0 TX complete handler.
646 SIGNAL(SIG_UART1_TRANS)
650 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
651 if (fifo_isempty(txfifo))
654 UARTDescs[SER_UART1].sending = false;
657 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
661 #endif /* SER_UART1_BUS_TXOFF */
663 #endif // AVR_HAS_UART1
667 * Serial 0 RX complete interrupt handler.
669 * This handler is interruptible.
670 * Interrupt are reenabled as soon as recv complete interrupt is
671 * disabled. Using INTERRUPT() is troublesome when the serial
672 * is heavily loaded, because an interrupt could be retriggered
673 * when executing the handler prologue before RXCIE is disabled.
675 SIGNAL(SIG_UART0_RECV)
679 /* Disable Recv complete IRQ */
680 UCSR0B &= ~BV(RXCIE);
683 /* Should be read before UDR */
684 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
686 /* To clear the RXC flag we must _always_ read the UDR even when we're
687 * not going to accept the incoming data, otherwise a new interrupt
688 * will occur once the handler terminates.
691 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
693 if (fifo_isfull(rxfifo))
694 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
697 fifo_push(rxfifo, c);
698 #if CONFIG_SER_HWHANDSHAKE
699 if (fifo_isfull(rxfifo))
704 /* Reenable receive complete int */
714 * Serial 1 RX complete interrupt handler.
716 * This handler is interruptible.
717 * Interrupt are reenabled as soon as recv complete interrupt is
718 * disabled. Using INTERRUPT() is troublesome when the serial
719 * is heavily loaded, because an interrupt could be retriggered
720 * when executing the handler prologue before RXCIE is disabled.
722 SIGNAL(SIG_UART1_RECV)
726 /* Disable Recv complete IRQ */
727 UCSR1B &= ~BV(RXCIE);
730 /* Should be read before UDR */
731 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
733 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
734 * not going to accept the incoming data
737 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
739 if (fifo_isfull(rxfifo))
740 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
743 fifo_push(rxfifo, c);
744 #if CONFIG_SER_HWHANDSHAKE
745 if (fifo_isfull(rxfifo))
749 /* Reenable receive complete int */
755 #endif // AVR_HAS_UART1
759 * SPI interrupt handler
763 /* Read incoming byte. */
764 if (!fifo_isfull(&ser_spi->rxfifo))
765 fifo_push(&ser_spi->rxfifo, SPDR);
769 ser_spi->status |= SERRF_RXFIFOOVERRUN;
773 if (!fifo_isempty(&ser_spi->txfifo))
774 SPDR = fifo_pop(&ser_spi->txfifo);
776 UARTDescs[SER_SPI].sending = false;