4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.34 2006/11/23 13:19:02 batt
42 *#* Add support for ATmega1281.
44 *#* Revision 1.33 2006/09/13 18:21:24 bernie
45 *#* Add configurable SPI pin mapping.
47 *#* Revision 1.32 2006/07/19 12:56:26 bernie
48 *#* Convert to new Doxygen style.
50 *#* Revision 1.31 2006/05/18 00:37:29 bernie
51 *#* Use hw_ser.h instead of ubiquitous hw.h.
53 *#* Revision 1.30 2006/02/17 22:23:06 bernie
54 *#* Update POSIX serial emulator.
56 *#* Revision 1.29 2005/11/27 23:31:48 bernie
57 *#* Support avr-libc 1.4.
59 *#* Revision 1.28 2005/11/04 16:20:02 bernie
60 *#* Fix reference to README.devlib in header.
62 *#* Revision 1.27 2005/07/03 15:19:31 bernie
65 *#* Revision 1.26 2005/04/11 19:10:27 bernie
66 *#* Include top-level headers from cfg/ subdir.
68 *#* Revision 1.25 2005/01/25 08:37:26 bernie
69 *#* CONFIG_SER_HWHANDSHAKE fixes.
71 *#* Revision 1.24 2005/01/14 00:49:16 aleph
72 *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
74 *#* Revision 1.23 2005/01/11 18:09:07 aleph
75 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
77 *#* Revision 1.22 2004/12/31 17:47:45 bernie
78 *#* Rename UNUSED() to UNUSED_ARG().
80 *#* Revision 1.21 2004/12/13 12:07:06 bernie
81 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
83 *#* Revision 1.20 2004/12/13 11:51:43 bernie
84 *#* Fix a latent bug with reentrant serial IRQs.
86 *#* Revision 1.19 2004/12/13 11:51:08 bernie
87 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
89 *#* Revision 1.18 2004/12/08 08:03:48 bernie
92 *#* Revision 1.17 2004/10/19 07:52:35 bernie
93 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
95 *#* Revision 1.16 2004/10/03 18:45:48 bernie
96 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
98 *#* Revision 1.15 2004/09/14 21:05:36 bernie
99 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
101 *#* Revision 1.14 2004/09/06 21:50:00 bernie
104 *#* Revision 1.13 2004/09/06 21:40:50 bernie
105 *#* Move buffer handling in chip-specific driver.
107 *#* Revision 1.12 2004/08/29 22:06:10 bernie
108 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
110 *#* Revision 1.10 2004/08/10 06:30:41 bernie
111 *#* Major redesign of serial bus policy handling.
113 *#* Revision 1.9 2004/08/02 20:20:29 aleph
114 *#* Merge from project_ks
116 *#* Revision 1.8 2004/07/29 22:57:09 bernie
117 *#* Several tweaks to reduce code size on ATmega8.
119 *#* Revision 1.7 2004/07/18 21:54:23 bernie
120 *#* Add ATmega8 support.
122 *#* Revision 1.5 2004/06/27 15:25:40 aleph
123 *#* Add missing callbacks for SPI;
124 *#* Change UNUSED() macro to new version with two args;
125 *#* Use TX line filling only on the correct KBUS serial port;
126 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
128 *#* Revision 1.4 2004/06/03 11:27:09 bernie
129 *#* Add dual-license information.
131 *#* Revision 1.3 2004/06/02 21:35:24 aleph
132 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
134 *#* Revision 1.2 2004/05/23 18:21:53 bernie
135 *#* Trim CVS logs and cleanup header info.
142 #include <hw_ser.h> /* Required for bus macros overrides */
143 #include <hw_cpu.h> /* CLOCK_FREQ */
144 #include <appconfig.h>
146 #include <cfg/debug.h>
147 #include <drv/timer.h>
148 #include <mware/fifobuf.h>
151 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
152 #include <avr/interrupt.h>
154 #include <avr/signal.h>
158 #if !CONFIG_SER_HWHANDSHAKE
160 * \name Hardware handshake (RTS/CTS).
163 #define RTS_ON do {} while (0)
164 #define RTS_OFF do {} while (0)
165 #define IS_CTS_ON true
166 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
170 #if CPU_AVR_ATMEGA1281
171 #define BIT_RXCIE0 RXCIE0
172 #define BIT_RXEN0 RXEN0
173 #define BIT_TXEN0 TXEN0
174 #define BIT_UDRIE0 UDRIE0
176 #define BIT_RXCIE1 RXCIE1
177 #define BIT_RXEN1 RXEN1
178 #define BIT_TXEN1 TXEN1
179 #define BIT_UDRIE1 UDRIE1
181 #define BIT_RXCIE0 RXCIE
182 #define BIT_RXEN0 RXEN
183 #define BIT_TXEN0 TXEN
184 #define BIT_UDRIE0 UDRIE
186 #define BIT_RXCIE1 RXCIE
187 #define BIT_RXEN1 RXEN
188 #define BIT_TXEN1 TXEN
189 #define BIT_UDRIE1 UDRIE
194 * \name Overridable serial bus hooks
196 * These can be redefined in hw.h to implement
197 * special bus policies such as half-duplex, 485, etc.
201 * TXBEGIN TXCHAR TXEND TXOFF
202 * | __________|__________ | |
205 * ______ __ __ __ __ __ __ ________________
206 * \/ \/ \/ \/ \/ \/ \/
207 * ______/\__/\__/\__/\__/\__/\__/
213 #ifndef SER_UART0_BUS_TXINIT
215 * Default TXINIT macro - invoked in uart0_init()
217 * - Enable both the receiver and the transmitter
218 * - Enable only the RX complete interrupt
220 #define SER_UART0_BUS_TXINIT do { \
221 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
225 #ifndef SER_UART0_BUS_TXBEGIN
227 * Invoked before starting a transmission
229 * - Enable both the receiver and the transmitter
230 * - Enable both the RX complete and UDR empty interrupts
232 #define SER_UART0_BUS_TXBEGIN do { \
233 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
237 #ifndef SER_UART0_BUS_TXCHAR
239 * Invoked to send one character.
241 #define SER_UART0_BUS_TXCHAR(c) do { \
246 #ifndef SER_UART0_BUS_TXEND
248 * Invoked as soon as the txfifo becomes empty
250 * - Keep both the receiver and the transmitter enabled
251 * - Keep the RX complete interrupt enabled
252 * - Disable the UDR empty interrupt
254 #define SER_UART0_BUS_TXEND do { \
255 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
259 #ifndef SER_UART0_BUS_TXOFF
261 * \def SER_UART0_BUS_TXOFF
263 * Invoked after the last character has been transmitted
265 * The default is no action.
268 #define SER_UART0_BUS_TXOFF
272 #ifndef SER_UART1_BUS_TXINIT
273 /** \sa SER_UART0_BUS_TXINIT */
274 #define SER_UART1_BUS_TXINIT do { \
275 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
278 #ifndef SER_UART1_BUS_TXBEGIN
279 /** \sa SER_UART0_BUS_TXBEGIN */
280 #define SER_UART1_BUS_TXBEGIN do { \
281 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
284 #ifndef SER_UART1_BUS_TXCHAR
285 /** \sa SER_UART0_BUS_TXCHAR */
286 #define SER_UART1_BUS_TXCHAR(c) do { \
290 #ifndef SER_UART1_BUS_TXEND
291 /** \sa SER_UART0_BUS_TXEND */
292 #define SER_UART1_BUS_TXEND do { \
293 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
296 #ifndef SER_UART1_BUS_TXOFF
298 * \def SER_UART1_BUS_TXOFF
300 * \see SER_UART0_BUS_TXOFF
303 #define SER_UART1_BUS_TXOFF
310 * \name Overridable SPI hooks
312 * These can be redefined in hw.h to implement
313 * special bus policies such as slave select pin handling, etc.
317 #ifndef SER_SPI_BUS_TXINIT
319 * Default TXINIT macro - invoked in spi_init()
320 * The default is no action.
322 #define SER_SPI_BUS_TXINIT
325 #ifndef SER_SPI_BUS_TXCLOSE
327 * Invoked after the last character has been transmitted.
328 * The default is no action.
330 #define SER_SPI_BUS_TXCLOSE
335 /* SPI port and pin configuration */
336 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
337 #define SPI_PORT PORTB
339 #define SPI_SS_BIT PB0
340 #define SPI_SCK_BIT PB1
341 #define SPI_MOSI_BIT PB2
342 #define SPI_MISO_BIT PB3
343 #elif CPU_AVR_ATMEGA8
344 #define SPI_PORT PORTB
346 #define SPI_SS_BIT PB2
347 #define SPI_SCK_BIT PB5
348 #define SPI_MOSI_BIT PB3
349 #define SPI_MISO_BIT PB4
351 #error Unknown architecture
354 /* USART register definitions */
355 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
356 #define AVR_HAS_UART1 1
357 #elif CPU_AVR_ATMEGA8
358 #define AVR_HAS_UART1 0
365 #define SIG_UART0_DATA SIG_UART_DATA
366 #define SIG_UART0_RECV SIG_UART_RECV
367 #define SIG_UART0_TRANS SIG_UART_TRANS
368 #elif CPU_AVR_ATMEGA103
369 #define AVR_HAS_UART1 0
374 #define SIG_UART0_DATA SIG_UART_DATA
375 #define SIG_UART0_RECV SIG_UART_RECV
376 #define SIG_UART0_TRANS SIG_UART_TRANS
378 #error Unknown architecture
383 * \def CONFIG_SER_STROBE
385 * This is a debug facility that can be used to
386 * monitor SER interrupt activity on an external pin.
388 * To use strobes, redefine the macros SER_STROBE_ON,
389 * SER_STROBE_OFF and SER_STROBE_INIT and set
390 * CONFIG_SER_STROBE to 1.
392 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
393 #define SER_STROBE_ON do {/*nop*/} while(0)
394 #define SER_STROBE_OFF do {/*nop*/} while(0)
395 #define SER_STROBE_INIT do {/*nop*/} while(0)
399 /* From the high-level serial driver */
400 extern struct Serial ser_handles[SER_CNT];
402 /* TX and RX buffers */
403 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
404 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
406 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
407 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
409 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
410 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
414 * Internal hardware state structure
416 * The \a sending variable is true while the transmission
417 * interrupt is retriggering itself.
419 * For the USARTs the \a sending flag is useful for taking specific
420 * actions before sending a burst of data, at the start of a trasmission
421 * but not before every char sent.
423 * For the SPI, this flag is necessary because the SPI sends and receives
424 * bytes at the same time and the SPI IRQ is unique for send/receive.
425 * The only way to start transmission is to write data in SPDR (this
426 * is done by spi_starttx()). We do this *only* if a transfer is
427 * not already started.
431 struct SerialHardware hw;
432 volatile bool sending;
437 * These are to trick GCC into *not* using absolute addressing mode
438 * when accessing ser_handles, which is very expensive.
440 * Accessing through these pointers generates much shorter
441 * (and hopefully faster) code.
443 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
445 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
447 struct Serial *ser_spi = &ser_handles[SER_SPI];
454 static void uart0_init(
455 UNUSED_ARG(struct SerialHardware *, _hw),
456 UNUSED_ARG(struct Serial *, ser))
458 SER_UART0_BUS_TXINIT;
463 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
468 static void uart0_enabletxirq(struct SerialHardware *_hw)
470 struct AvrSerial *hw = (struct AvrSerial *)_hw;
473 * WARNING: racy code here! The tx interrupt sets hw->sending to false
474 * when it runs with an empty fifo. The order of statements in the
480 SER_UART0_BUS_TXBEGIN;
484 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
486 /* Compute baud-rate period */
487 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
489 #if !CPU_AVR_ATMEGA103
490 UBRR0H = (period) >> 8;
494 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
497 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
499 #if !CPU_AVR_ATMEGA103
500 UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
506 static void uart1_init(
507 UNUSED_ARG(struct SerialHardware *, _hw),
508 UNUSED_ARG(struct Serial *, ser))
510 SER_UART1_BUS_TXINIT;
515 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
520 static void uart1_enabletxirq(struct SerialHardware *_hw)
522 struct AvrSerial *hw = (struct AvrSerial *)_hw;
525 * WARNING: racy code here! The tx interrupt
526 * sets hw->sending to false when it runs with
527 * an empty fifo. The order of the statements
528 * in the if-block matters.
533 SER_UART1_BUS_TXBEGIN;
537 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
539 /* Compute baud-rate period */
540 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
542 UBRR1H = (period) >> 8;
545 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
548 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
550 UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
553 #endif // AVR_HAS_UART1
555 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
558 * Set MOSI and SCK ports out, MISO in.
560 * The ATmega64/128 datasheet explicitly states that the input/output
561 * state of the SPI pins is not significant, as when the SPI is
562 * active the I/O port are overrided.
563 * This is *blatantly FALSE*.
565 * Moreover, the MISO pin on the board_kc *must* be in high impedance
566 * state even when the SPI is off, because the line is wired together
567 * with the KBus serial RX, and the transmitter of the slave boards
568 * would be unable to drive the line.
570 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
573 * If the SPI master mode is activated and the SS pin is in input and tied low,
574 * the SPI hardware will automatically switch to slave mode!
575 * For proper communication this pins should therefore be:
577 * - as input but tied high forever!
578 * This driver set the pin as output.
580 #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
581 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
583 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
584 /* Enable SPI, IRQ on, Master */
585 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
588 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
592 /* Set SPI clock rate */
593 #if CONFIG_SPI_CLOCK_DIV == 128
594 SPCR |= (BV(SPR1) | BV(SPR0));
595 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
597 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
599 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
600 // SPR0 & SDPR1 both at 0
602 #error Unsupported SPI clock division factor.
605 /* Set SPI2X bit (spi double frequency) */
606 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
607 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
609 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
612 #error Unsupported SPI clock division factor.
615 /* Set clock polarity */
616 #if CONFIG_SPI_CLOCK_POL == 1
620 /* Set clock phase */
621 #if CONFIG_SPI_CLOCK_PHASE == 1
629 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
635 /* Set all pins as inputs */
636 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
639 static void spi_starttx(struct SerialHardware *_hw)
641 struct AvrSerial *hw = (struct AvrSerial *)_hw;
644 IRQ_SAVE_DISABLE(flags);
646 /* Send data only if the SPI is not already transmitting */
647 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
650 SPDR = fifo_pop(&ser_spi->txfifo);
656 static void spi_setbaudrate(
657 UNUSED_ARG(struct SerialHardware *, _hw),
658 UNUSED_ARG(unsigned long, rate))
663 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
668 static bool tx_sending(struct SerialHardware* _hw)
670 struct AvrSerial *hw = (struct AvrSerial *)_hw;
676 // FIXME: move into compiler.h? Ditch?
678 #define C99INIT(name,val) .name = val
679 #elif defined(__GNUC__)
680 #define C99INIT(name,val) name: val
682 #warning No designated initializers, double check your code
683 #define C99INIT(name,val) (val)
687 * High-level interface data structures
689 static const struct SerialHardwareVT UART0_VT =
691 C99INIT(init, uart0_init),
692 C99INIT(cleanup, uart0_cleanup),
693 C99INIT(setBaudrate, uart0_setbaudrate),
694 C99INIT(setParity, uart0_setparity),
695 C99INIT(txStart, uart0_enabletxirq),
696 C99INIT(txSending, tx_sending),
700 static const struct SerialHardwareVT UART1_VT =
702 C99INIT(init, uart1_init),
703 C99INIT(cleanup, uart1_cleanup),
704 C99INIT(setBaudrate, uart1_setbaudrate),
705 C99INIT(setParity, uart1_setparity),
706 C99INIT(txStart, uart1_enabletxirq),
707 C99INIT(txSending, tx_sending),
709 #endif // AVR_HAS_UART1
711 static const struct SerialHardwareVT SPI_VT =
713 C99INIT(init, spi_init),
714 C99INIT(cleanup, spi_cleanup),
715 C99INIT(setBaudrate, spi_setbaudrate),
716 C99INIT(setParity, spi_setparity),
717 C99INIT(txStart, spi_starttx),
718 C99INIT(txSending, tx_sending),
721 static struct AvrSerial UARTDescs[SER_CNT] =
725 C99INIT(table, &UART0_VT),
726 C99INIT(txbuffer, uart0_txbuffer),
727 C99INIT(rxbuffer, uart0_rxbuffer),
728 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
729 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
731 C99INIT(sending, false),
736 C99INIT(table, &UART1_VT),
737 C99INIT(txbuffer, uart1_txbuffer),
738 C99INIT(rxbuffer, uart1_rxbuffer),
739 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
740 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
742 C99INIT(sending, false),
747 C99INIT(table, &SPI_VT),
748 C99INIT(txbuffer, spi_txbuffer),
749 C99INIT(rxbuffer, spi_rxbuffer),
750 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
751 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
753 C99INIT(sending, false),
757 struct SerialHardware *ser_hw_getdesc(int unit)
759 ASSERT(unit < SER_CNT);
760 return &UARTDescs[unit].hw;
768 #if CONFIG_SER_HWHANDSHAKE
770 /// This interrupt is triggered when the CTS line goes high
773 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
774 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
775 EIMSK &= ~EIMSKF_CTS;
778 #endif // CONFIG_SER_HWHANDSHAKE
782 * Serial 0 TX interrupt handler
784 SIGNAL(USART0_UDRE_vect)
788 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
790 if (fifo_isempty(txfifo))
793 #ifndef SER_UART0_BUS_TXOFF
794 UARTDescs[SER_UART0].sending = false;
797 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
800 // Disable rx interrupt and tx, enable CTS interrupt
802 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
809 char c = fifo_pop(txfifo);
810 SER_UART0_BUS_TXCHAR(c);
816 #ifdef SER_UART0_BUS_TXOFF
818 * Serial port 0 TX complete interrupt handler.
820 * This IRQ is usually disabled. The UDR-empty interrupt
821 * enables it when there's no more data to transmit.
822 * We need to wait until the last character has been
823 * transmitted before switching the 485 transceiver to
826 * The txfifo might have been refilled by putchar() while
827 * we were waiting for the transmission complete interrupt.
828 * In this case, we must restart the UDR empty interrupt,
829 * otherwise we'd stop the serial port with some data
830 * still pending in the buffer.
832 SIGNAL(SIG_UART0_TRANS)
836 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
837 if (fifo_isempty(txfifo))
840 UARTDescs[SER_UART0].sending = false;
843 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
847 #endif /* SER_UART0_BUS_TXOFF */
853 * Serial 1 TX interrupt handler
855 SIGNAL(USART1_UDRE_vect)
859 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
861 if (fifo_isempty(txfifo))
864 #ifndef SER_UART1_BUS_TXOFF
865 UARTDescs[SER_UART1].sending = false;
868 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
871 // Disable rx interrupt and tx, enable CTS interrupt
873 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
880 char c = fifo_pop(txfifo);
881 SER_UART1_BUS_TXCHAR(c);
887 #ifdef SER_UART1_BUS_TXOFF
889 * Serial port 1 TX complete interrupt handler.
891 * \sa port 0 TX complete handler.
893 SIGNAL(SIG_UART1_TRANS)
897 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
898 if (fifo_isempty(txfifo))
901 UARTDescs[SER_UART1].sending = false;
904 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
908 #endif /* SER_UART1_BUS_TXOFF */
910 #endif // AVR_HAS_UART1
914 * Serial 0 RX complete interrupt handler.
916 * This handler is interruptible.
917 * Interrupt are reenabled as soon as recv complete interrupt is
918 * disabled. Using INTERRUPT() is troublesome when the serial
919 * is heavily loaded, because an interrupt could be retriggered
920 * when executing the handler prologue before RXCIE is disabled.
922 * \note The code that re-enables interrupts is commented out
923 * because in some nasty cases the interrupt is retriggered.
924 * This is probably due to the RXC flag being set before
925 * RXCIE is cleared. Unfortunately the RXC flag is read-only
926 * and can't be cleared by code.
928 SIGNAL(USART0_RX_vect)
932 /* Disable Recv complete IRQ */
933 //UCSR0B &= ~BV(RXCIE);
936 /* Should be read before UDR */
937 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
939 /* To clear the RXC flag we must _always_ read the UDR even when we're
940 * not going to accept the incoming data, otherwise a new interrupt
941 * will occur once the handler terminates.
944 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
946 if (fifo_isfull(rxfifo))
947 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
950 fifo_push(rxfifo, c);
951 #if CONFIG_SER_HWHANDSHAKE
952 if (fifo_isfull(rxfifo))
957 /* Reenable receive complete int */
959 //UCSR0B |= BV(RXCIE);
968 * Serial 1 RX complete interrupt handler.
970 * This handler is interruptible.
971 * Interrupt are reenabled as soon as recv complete interrupt is
972 * disabled. Using INTERRUPT() is troublesome when the serial
973 * is heavily loaded, because an interrupt could be retriggered
974 * when executing the handler prologue before RXCIE is disabled.
976 * \see SIGNAL(USART1_RX_vect)
978 SIGNAL(USART1_RX_vect)
982 /* Disable Recv complete IRQ */
983 //UCSR1B &= ~BV(RXCIE);
986 /* Should be read before UDR */
987 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
989 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
990 * not going to accept the incoming data
993 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
994 //ASSERT_VALID_FIFO(rxfifo);
996 if (UNLIKELY(fifo_isfull(rxfifo)))
997 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
1000 fifo_push(rxfifo, c);
1001 #if CONFIG_SER_HWHANDSHAKE
1002 if (fifo_isfull(rxfifo))
1006 /* Re-enable receive complete int */
1008 //UCSR1B |= BV(RXCIE);
1013 #endif // AVR_HAS_UART1
1017 * SPI interrupt handler
1023 /* Read incoming byte. */
1024 if (!fifo_isfull(&ser_spi->rxfifo))
1025 fifo_push(&ser_spi->rxfifo, SPDR);
1029 ser_spi->status |= SERRF_RXFIFOOVERRUN;
1033 if (!fifo_isempty(&ser_spi->txfifo))
1034 SPDR = fifo_pop(&ser_spi->txfifo);
1036 UARTDescs[SER_SPI].sending = false;