4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.31 2006/05/18 00:37:29 bernie
42 *#* Use hw_ser.h instead of ubiquitous hw.h.
44 *#* Revision 1.30 2006/02/17 22:23:06 bernie
45 *#* Update POSIX serial emulator.
47 *#* Revision 1.29 2005/11/27 23:31:48 bernie
48 *#* Support avr-libc 1.4.
50 *#* Revision 1.28 2005/11/04 16:20:02 bernie
51 *#* Fix reference to README.devlib in header.
53 *#* Revision 1.27 2005/07/03 15:19:31 bernie
56 *#* Revision 1.26 2005/04/11 19:10:27 bernie
57 *#* Include top-level headers from cfg/ subdir.
59 *#* Revision 1.25 2005/01/25 08:37:26 bernie
60 *#* CONFIG_SER_HWHANDSHAKE fixes.
62 *#* Revision 1.24 2005/01/14 00:49:16 aleph
63 *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
65 *#* Revision 1.23 2005/01/11 18:09:07 aleph
66 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
68 *#* Revision 1.22 2004/12/31 17:47:45 bernie
69 *#* Rename UNUSED() to UNUSED_ARG().
71 *#* Revision 1.21 2004/12/13 12:07:06 bernie
72 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
74 *#* Revision 1.20 2004/12/13 11:51:43 bernie
75 *#* Fix a latent bug with reentrant serial IRQs.
77 *#* Revision 1.19 2004/12/13 11:51:08 bernie
78 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
80 *#* Revision 1.18 2004/12/08 08:03:48 bernie
83 *#* Revision 1.17 2004/10/19 07:52:35 bernie
84 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
86 *#* Revision 1.16 2004/10/03 18:45:48 bernie
87 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
89 *#* Revision 1.15 2004/09/14 21:05:36 bernie
90 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
92 *#* Revision 1.14 2004/09/06 21:50:00 bernie
95 *#* Revision 1.13 2004/09/06 21:40:50 bernie
96 *#* Move buffer handling in chip-specific driver.
98 *#* Revision 1.12 2004/08/29 22:06:10 bernie
99 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
101 *#* Revision 1.10 2004/08/10 06:30:41 bernie
102 *#* Major redesign of serial bus policy handling.
104 *#* Revision 1.9 2004/08/02 20:20:29 aleph
105 *#* Merge from project_ks
107 *#* Revision 1.8 2004/07/29 22:57:09 bernie
108 *#* Several tweaks to reduce code size on ATmega8.
110 *#* Revision 1.7 2004/07/18 21:54:23 bernie
111 *#* Add ATmega8 support.
113 *#* Revision 1.5 2004/06/27 15:25:40 aleph
114 *#* Add missing callbacks for SPI;
115 *#* Change UNUSED() macro to new version with two args;
116 *#* Use TX line filling only on the correct KBUS serial port;
117 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
119 *#* Revision 1.4 2004/06/03 11:27:09 bernie
120 *#* Add dual-license information.
122 *#* Revision 1.3 2004/06/02 21:35:24 aleph
123 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
125 *#* Revision 1.2 2004/05/23 18:21:53 bernie
126 *#* Trim CVS logs and cleanup header info.
132 #include "hw_ser.h" /* Required for bus macros overrides */
133 #include <appconfig.h>
135 #include <cfg/debug.h>
136 #include <drv/timer.h>
137 #include <mware/fifobuf.h>
140 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
141 #include <avr/interrupt.h>
143 #include <avr/signal.h>
147 #if !CONFIG_SER_HWHANDSHAKE
149 * \name Hardware handshake (RTS/CTS).
152 #define RTS_ON do {} while (0)
153 #define RTS_OFF do {} while (0)
154 #define IS_CTS_ON true
155 #define EIMSKF_CTS 0 /*!< Dummy value, must be overridden */
161 * \name Overridable serial bus hooks
163 * These can be redefined in hw.h to implement
164 * special bus policies such as half-duplex, 485, etc.
168 * TXBEGIN TXCHAR TXEND TXOFF
169 * | __________|__________ | |
172 * ______ __ __ __ __ __ __ ________________
173 * \/ \/ \/ \/ \/ \/ \/
174 * ______/\__/\__/\__/\__/\__/\__/
180 #ifndef SER_UART0_BUS_TXINIT
182 * Default TXINIT macro - invoked in uart0_init()
184 * - Enable both the receiver and the transmitter
185 * - Enable only the RX complete interrupt
187 #define SER_UART0_BUS_TXINIT do { \
188 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
192 #ifndef SER_UART0_BUS_TXBEGIN
194 * Invoked before starting a transmission
196 * - Enable both the receiver and the transmitter
197 * - Enable both the RX complete and UDR empty interrupts
199 #define SER_UART0_BUS_TXBEGIN do { \
200 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
204 #ifndef SER_UART0_BUS_TXCHAR
206 * Invoked to send one character.
208 #define SER_UART0_BUS_TXCHAR(c) do { \
213 #ifndef SER_UART0_BUS_TXEND
215 * Invoked as soon as the txfifo becomes empty
217 * - Keep both the receiver and the transmitter enabled
218 * - Keep the RX complete interrupt enabled
219 * - Disable the UDR empty interrupt
221 #define SER_UART0_BUS_TXEND do { \
222 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
226 #ifndef SER_UART0_BUS_TXOFF
228 * \def SER_UART0_BUS_TXOFF
230 * Invoked after the last character has been transmitted
232 * The default is no action.
235 #define SER_UART0_BUS_TXOFF
239 #ifndef SER_UART1_BUS_TXINIT
240 /*! \sa SER_UART0_BUS_TXINIT */
241 #define SER_UART1_BUS_TXINIT do { \
242 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
245 #ifndef SER_UART1_BUS_TXBEGIN
246 /*! \sa SER_UART0_BUS_TXBEGIN */
247 #define SER_UART1_BUS_TXBEGIN do { \
248 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
251 #ifndef SER_UART1_BUS_TXCHAR
252 /*! \sa SER_UART0_BUS_TXCHAR */
253 #define SER_UART1_BUS_TXCHAR(c) do { \
257 #ifndef SER_UART1_BUS_TXEND
258 /*! \sa SER_UART0_BUS_TXEND */
259 #define SER_UART1_BUS_TXEND do { \
260 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
263 #ifndef SER_UART1_BUS_TXOFF
265 * \def SER_UART1_BUS_TXOFF
267 * \see SER_UART0_BUS_TXOFF
270 #define SER_UART1_BUS_TXOFF
277 * \name Overridable SPI hooks
279 * These can be redefined in hw.h to implement
280 * special bus policies such as slave select pin handling, etc.
284 #ifndef SER_SPI_BUS_TXINIT
286 * Default TXINIT macro - invoked in spi_init()
287 * The default is no action.
289 #define SER_SPI_BUS_TXINIT
292 #ifndef SER_SPI_BUS_TXCLOSE
294 * Invoked after the last character has been transmitted.
295 * The default is no action.
297 #define SER_SPI_BUS_TXCLOSE
302 /* SPI port and pin configuration */
303 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
304 #define SPI_PORT PORTB
306 #define SPI_SCK_BIT PB1
307 #define SPI_MOSI_BIT PB2
308 #define SPI_MISO_BIT PB3
309 #elif CPU_AVR_ATMEGA8
310 #define SPI_PORT PORTB
312 #define SPI_SCK_BIT PB5
313 #define SPI_MOSI_BIT PB3
314 #define SPI_MISO_BIT PB4
316 #error Unknown architecture
319 /* USART register definitions */
320 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
321 #define AVR_HAS_UART1 1
322 #elif CPU_AVR_ATMEGA8
323 #define AVR_HAS_UART1 0
330 #define SIG_UART0_DATA SIG_UART_DATA
331 #define SIG_UART0_RECV SIG_UART_RECV
332 #define SIG_UART0_TRANS SIG_UART_TRANS
333 #elif CPU_AVR_ATMEGA103
334 #define AVR_HAS_UART1 0
339 #define SIG_UART0_DATA SIG_UART_DATA
340 #define SIG_UART0_RECV SIG_UART_RECV
341 #define SIG_UART0_TRANS SIG_UART_TRANS
343 #error Unknown architecture
348 * \def CONFIG_SER_STROBE
350 * This is a debug facility that can be used to
351 * monitor SER interrupt activity on an external pin.
353 * To use strobes, redefine the macros SER_STROBE_ON,
354 * SER_STROBE_OFF and SER_STROBE_INIT and set
355 * CONFIG_SER_STROBE to 1.
357 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
358 #define SER_STROBE_ON do {/*nop*/} while(0)
359 #define SER_STROBE_OFF do {/*nop*/} while(0)
360 #define SER_STROBE_INIT do {/*nop*/} while(0)
364 /* From the high-level serial driver */
365 extern struct Serial ser_handles[SER_CNT];
367 /* TX and RX buffers */
368 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
369 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
371 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
372 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
374 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
375 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
379 * Internal hardware state structure
381 * The \a sending variable is true while the transmission
382 * interrupt is retriggering itself.
384 * For the USARTs the \a sending flag is useful for taking specific
385 * actions before sending a burst of data, at the start of a trasmission
386 * but not before every char sent.
388 * For the SPI, this flag is necessary because the SPI sends and receives
389 * bytes at the same time and the SPI IRQ is unique for send/receive.
390 * The only way to start transmission is to write data in SPDR (this
391 * is done by spi_starttx()). We do this *only* if a transfer is
392 * not already started.
396 struct SerialHardware hw;
397 volatile bool sending;
402 * These are to trick GCC into *not* using absolute addressing mode
403 * when accessing ser_handles, which is very expensive.
405 * Accessing through these pointers generates much shorter
406 * (and hopefully faster) code.
408 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
410 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
412 struct Serial *ser_spi = &ser_handles[SER_SPI];
419 static void uart0_init(
420 UNUSED_ARG(struct SerialHardware *, _hw),
421 UNUSED_ARG(struct Serial *, ser))
423 SER_UART0_BUS_TXINIT;
428 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
433 static void uart0_enabletxirq(struct SerialHardware *_hw)
435 struct AvrSerial *hw = (struct AvrSerial *)_hw;
438 * WARNING: racy code here! The tx interrupt sets hw->sending to false
439 * when it runs with an empty fifo. The order of statements in the
445 SER_UART0_BUS_TXBEGIN;
449 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
451 /* Compute baud-rate period */
452 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
454 #if !CPU_AVR_ATMEGA103
455 UBRR0H = (period) >> 8;
459 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
462 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
464 #if !CPU_AVR_ATMEGA103
465 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
471 static void uart1_init(
472 UNUSED_ARG(struct SerialHardware *, _hw),
473 UNUSED_ARG(struct Serial *, ser))
475 SER_UART1_BUS_TXINIT;
480 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
485 static void uart1_enabletxirq(struct SerialHardware *_hw)
487 struct AvrSerial *hw = (struct AvrSerial *)_hw;
490 * WARNING: racy code here! The tx interrupt
491 * sets hw->sending to false when it runs with
492 * an empty fifo. The order of the statements
493 * in the if-block matters.
498 SER_UART1_BUS_TXBEGIN;
502 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
504 /* Compute baud-rate period */
505 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
507 UBRR1H = (period) >> 8;
510 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
513 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
515 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
518 #endif // AVR_HAS_UART1
520 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
523 * Set MOSI and SCK ports out, MISO in.
525 * The ATmega64/128 datasheet explicitly states that the input/output
526 * state of the SPI pins is not significant, as when the SPI is
527 * active the I/O port are overrided.
528 * This is *blatantly FALSE*.
530 * Moreover, the MISO pin on the board_kc *must* be in high impedance
531 * state even when the SPI is off, because the line is wired together
532 * with the KBus serial RX, and the transmitter of the slave boards
533 * would be unable to drive the line.
535 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
536 SPI_DDR &= ~BV(SPI_MISO_BIT);
537 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
538 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
545 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
551 /* Set all pins as inputs */
552 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
555 static void spi_starttx(struct SerialHardware *_hw)
557 struct AvrSerial *hw = (struct AvrSerial *)_hw;
560 IRQ_SAVE_DISABLE(flags);
562 /* Send data only if the SPI is not already transmitting */
563 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
566 SPDR = fifo_pop(&ser_spi->txfifo);
572 static void spi_setbaudrate(
573 UNUSED_ARG(struct SerialHardware *, _hw),
574 UNUSED_ARG(unsigned long, rate))
579 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
584 static bool tx_sending(struct SerialHardware* _hw)
586 struct AvrSerial *hw = (struct AvrSerial *)_hw;
592 // FIXME: move into compiler.h? Ditch?
594 #define C99INIT(name,val) .name = val
595 #elif defined(__GNUC__)
596 #define C99INIT(name,val) name: val
598 #warning No designated initializers, double check your code
599 #define C99INIT(name,val) (val)
603 * High-level interface data structures
605 static const struct SerialHardwareVT UART0_VT =
607 C99INIT(init, uart0_init),
608 C99INIT(cleanup, uart0_cleanup),
609 C99INIT(setBaudrate, uart0_setbaudrate),
610 C99INIT(setParity, uart0_setparity),
611 C99INIT(txStart, uart0_enabletxirq),
612 C99INIT(txSending, tx_sending),
616 static const struct SerialHardwareVT UART1_VT =
618 C99INIT(init, uart1_init),
619 C99INIT(cleanup, uart1_cleanup),
620 C99INIT(setBaudrate, uart1_setbaudrate),
621 C99INIT(setParity, uart1_setparity),
622 C99INIT(txStart, uart1_enabletxirq),
623 C99INIT(txSending, tx_sending),
625 #endif // AVR_HAS_UART1
627 static const struct SerialHardwareVT SPI_VT =
629 C99INIT(init, spi_init),
630 C99INIT(cleanup, spi_cleanup),
631 C99INIT(setBaudrate, spi_setbaudrate),
632 C99INIT(setParity, spi_setparity),
633 C99INIT(txStart, spi_starttx),
634 C99INIT(txSending, tx_sending),
637 static struct AvrSerial UARTDescs[SER_CNT] =
641 C99INIT(table, &UART0_VT),
642 C99INIT(txbuffer, uart0_txbuffer),
643 C99INIT(rxbuffer, uart0_rxbuffer),
644 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
645 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
647 C99INIT(sending, false),
652 C99INIT(table, &UART1_VT),
653 C99INIT(txbuffer, uart1_txbuffer),
654 C99INIT(rxbuffer, uart1_rxbuffer),
655 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
656 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
658 C99INIT(sending, false),
663 C99INIT(table, &SPI_VT),
664 C99INIT(txbuffer, spi_txbuffer),
665 C99INIT(rxbuffer, spi_rxbuffer),
666 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
667 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
669 C99INIT(sending, false),
673 struct SerialHardware *ser_hw_getdesc(int unit)
675 ASSERT(unit < SER_CNT);
676 return &UARTDescs[unit].hw;
684 #if CONFIG_SER_HWHANDSHAKE
686 //! This interrupt is triggered when the CTS line goes high
689 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
690 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
691 EIMSK &= ~EIMSKF_CTS;
694 #endif // CONFIG_SER_HWHANDSHAKE
698 * Serial 0 TX interrupt handler
700 SIGNAL(SIG_UART0_DATA)
704 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
706 if (fifo_isempty(txfifo))
709 #ifndef SER_UART0_BUS_TXOFF
710 UARTDescs[SER_UART0].sending = false;
713 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
716 // Disable rx interrupt and tx, enable CTS interrupt
718 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
725 char c = fifo_pop(txfifo);
726 SER_UART0_BUS_TXCHAR(c);
732 #ifdef SER_UART0_BUS_TXOFF
734 * Serial port 0 TX complete interrupt handler.
736 * This IRQ is usually disabled. The UDR-empty interrupt
737 * enables it when there's no more data to transmit.
738 * We need to wait until the last character has been
739 * transmitted before switching the 485 transceiver to
742 * The txfifo might have been refilled by putchar() while
743 * we were waiting for the transmission complete interrupt.
744 * In this case, we must restart the UDR empty interrupt,
745 * otherwise we'd stop the serial port with some data
746 * still pending in the buffer.
748 SIGNAL(SIG_UART0_TRANS)
752 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
753 if (fifo_isempty(txfifo))
756 UARTDescs[SER_UART0].sending = false;
759 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
763 #endif /* SER_UART0_BUS_TXOFF */
769 * Serial 1 TX interrupt handler
771 SIGNAL(SIG_UART1_DATA)
775 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
777 if (fifo_isempty(txfifo))
780 #ifndef SER_UART1_BUS_TXOFF
781 UARTDescs[SER_UART1].sending = false;
784 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
787 // Disable rx interrupt and tx, enable CTS interrupt
789 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
796 char c = fifo_pop(txfifo);
797 SER_UART1_BUS_TXCHAR(c);
803 #ifdef SER_UART1_BUS_TXOFF
805 * Serial port 1 TX complete interrupt handler.
807 * \sa port 0 TX complete handler.
809 SIGNAL(SIG_UART1_TRANS)
813 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
814 if (fifo_isempty(txfifo))
817 UARTDescs[SER_UART1].sending = false;
820 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
824 #endif /* SER_UART1_BUS_TXOFF */
826 #endif // AVR_HAS_UART1
830 * Serial 0 RX complete interrupt handler.
832 * This handler is interruptible.
833 * Interrupt are reenabled as soon as recv complete interrupt is
834 * disabled. Using INTERRUPT() is troublesome when the serial
835 * is heavily loaded, because an interrupt could be retriggered
836 * when executing the handler prologue before RXCIE is disabled.
838 * \note The code that re-enables interrupts is commented out
839 * because in some nasty cases the interrupt is retriggered.
840 * This is probably due to the RXC flag being set before
841 * RXCIE is cleared. Unfortunately the RXC flag is read-only
842 * and can't be cleared by code.
844 SIGNAL(SIG_UART0_RECV)
848 /* Disable Recv complete IRQ */
849 //UCSR0B &= ~BV(RXCIE);
852 /* Should be read before UDR */
853 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
855 /* To clear the RXC flag we must _always_ read the UDR even when we're
856 * not going to accept the incoming data, otherwise a new interrupt
857 * will occur once the handler terminates.
860 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
862 if (fifo_isfull(rxfifo))
863 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
866 fifo_push(rxfifo, c);
867 #if CONFIG_SER_HWHANDSHAKE
868 if (fifo_isfull(rxfifo))
873 /* Reenable receive complete int */
875 //UCSR0B |= BV(RXCIE);
884 * Serial 1 RX complete interrupt handler.
886 * This handler is interruptible.
887 * Interrupt are reenabled as soon as recv complete interrupt is
888 * disabled. Using INTERRUPT() is troublesome when the serial
889 * is heavily loaded, because an interrupt could be retriggered
890 * when executing the handler prologue before RXCIE is disabled.
892 * \see SIGNAL(SIG_UART0_RECV)
894 SIGNAL(SIG_UART1_RECV)
898 /* Disable Recv complete IRQ */
899 //UCSR1B &= ~BV(RXCIE);
902 /* Should be read before UDR */
903 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
905 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
906 * not going to accept the incoming data
909 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
910 //ASSERT_VALID_FIFO(rxfifo);
912 if (UNLIKELY(fifo_isfull(rxfifo)))
913 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
916 fifo_push(rxfifo, c);
917 #if CONFIG_SER_HWHANDSHAKE
918 if (fifo_isfull(rxfifo))
922 /* Re-enable receive complete int */
924 //UCSR1B |= BV(RXCIE);
929 #endif // AVR_HAS_UART1
933 * SPI interrupt handler
939 /* Read incoming byte. */
940 if (!fifo_isfull(&ser_spi->rxfifo))
941 fifo_push(&ser_spi->rxfifo, SPDR);
945 ser_spi->status |= SERRF_RXFIFOOVERRUN;
949 if (!fifo_isempty(&ser_spi->txfifo))
950 SPDR = fifo_pop(&ser_spi->txfifo);
952 UARTDescs[SER_SPI].sending = false;