4 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
5 * Copyright 2003,2004 Develer S.r.l. (http://www.develer.com/)
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
40 * Revision 1.7 2004/07/18 21:54:23 bernie
41 * Add ATmega8 support.
43 * Revision 1.5 2004/06/27 15:25:40 aleph
44 * Add missing callbacks for SPI;
45 * Change UNUSED() macro to new version with two args;
46 * Use TX line filling only on the correct KBUS serial port;
47 * Fix nasty IRQ disabling bug in recv complete hander for port 1.
49 * Revision 1.4 2004/06/03 11:27:09 bernie
50 * Add dual-license information.
52 * Revision 1.3 2004/06/02 21:35:24 aleph
53 * Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
55 * Revision 1.2 2004/05/23 18:21:53 bernie
56 * Trim CVS logs and cleanup header info.
65 #include <mware/fifobuf.h>
67 #include <avr/signal.h>
70 extern struct Serial ser_handles[SER_CNT];
74 struct SerialHardware hw;
75 struct Serial* serial;
79 /* Hardware handshake */
82 #define IS_CTS_ON true
83 #define IS_CTS_OFF false
86 /* SPI port and pin configuration */
87 #define SPI_PORT PORTB
89 #define SPI_SCK_BIT PORTB1
90 #define SPI_MOSI_BIT PORTB2
91 #define SPI_MISO_BIT PORTB3
94 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
96 #elif defined(__AVR_ATmega8__)
103 #define SIG_UART0_DATA SIG_UART_DATA
104 #define SIG_UART0_RECV SIG_UART_RECV
105 #elif defined(__AVR_ATmega103__)
106 /* Macro for ATmega103 compatibility */
111 #define SIG_UART0_DATA SIG_UART_DATA
112 #define SIG_UART0_RECV SIG_UART_RECV
114 #error Unknown architecture
118 /* Transmission fill byte */
119 #define SER_FILL_BYTE 0xAA
122 static void uart0_enabletxirq(UNUSED(struct SerialHardware *, ctx))
124 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
125 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
127 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
131 static void uart0_init(struct SerialHardware *_hw, struct Serial *ser)
133 struct AvrSerial *hw = (struct AvrSerial *)_hw;
136 #if defined(ARCH_BOARD_KS) && (ARCH & ARCH_BOARD_KS)
137 /* Set TX port as input with pull-up enabled to avoid
138 noise on the remote RX when TX is disabled. */
140 DISABLE_IRQSAVE(flags);
143 ENABLE_IRQRESTORE(flags);
144 #endif /* ARCH_BOARD_KS */
146 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
148 * Set multiprocessor mode and 9 bit data frame.
149 * The receiver keep MPCM bit always on. When useful data
150 * is trasmitted the ninth bit is set and the receiver receive
152 * When useless fill bytes are sent the ninth bit is cleared
153 * and the receiver will ignore them.
156 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
158 UCSR0B = BV(RXCIE) | BV(RXEN);
164 static void uart0_cleanup(UNUSED(struct SerialHardware *, ctx))
169 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, ctx), unsigned long rate)
171 /* Compute baud-rate period */
172 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
173 DB(kprintf("uart0_setbaudrate(rate=%ld): period=%d\n", rate, period);)
175 #ifndef __AVR_ATmega103__
176 UBRR0H = (period) >> 8;
181 static void uart0_setparity(UNUSED(struct SerialHardware *, ctx), int parity)
183 #ifndef __AVR_ATmega103__
184 UCSR0C |= (parity) << UPM0;
190 static void uart1_enabletxirq(UNUSED(struct SerialHardware *, ctx))
192 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
193 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
195 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
199 static void uart1_init(struct SerialHardware *_hw, struct Serial *ser)
201 struct AvrSerial *hw = (struct AvrSerial *)_hw;
204 /* Set TX port as input with pull-up enabled to avoid
205 * noise on the remote RX when TX is disabled */
207 DISABLE_IRQSAVE(flags);
210 ENABLE_IRQRESTORE(flags);
212 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
213 /*! See comment in uart0_init() */
215 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
217 UCSR1B = BV(RXCIE) | BV(RXEN);
223 static void uart1_cleanup(UNUSED(struct SerialHardware *, ctx))
228 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, ctx), unsigned long rate)
230 /* Compute baud-rate period */
231 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
232 DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
234 UBRR1H = (period) >> 8;
238 static void uart1_setparity(UNUSED(struct SerialHardware *, ctx), int parity)
240 // FIXME: move somewhere else
241 UCSR1C |= BV(USBS1); // 2 stop bits
242 UCSR1C |= (parity) << UPM0;
245 #endif // AVR_HAS_UART1
248 static void spi_init(struct SerialHardware *_hw, struct Serial *ser)
250 struct AvrSerial *hw = (struct AvrSerial *)_hw;
254 * Set MOSI and SCK ports out, MISO in.
256 * The ATmega64/128 datasheet explicitly states that the input/output
257 * state of the SPI pins is not significant, as when the SPI is
258 * active the I/O port are overrided.
259 * This is *blatantly FALSE*.
261 * Moreover the MISO pin on the board_kc *must* be in high impedance
262 * state even when the SPI is off, because the line is wired together
263 * with the KBus serial RX, and the transmitter of the slave boards
264 * could not be able to drive the line.
266 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
267 SPI_DDR &= ~BV(SPI_MISO_BIT);
268 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
269 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
272 static void spi_cleanup(UNUSED(struct SerialHardware *, ctx))
275 /* Set all pins as inputs */
276 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
279 static void spi_setbaudrate(UNUSED(struct SerialHardware *, ctx), UNUSED(unsigned long, rate))
284 static void spi_setparity(UNUSED(struct SerialHardware *, ctx), UNUSED(int, parity))
290 #if defined(CONFIG_SER_HW_HANDSHAKE)
292 //! This interrupt is triggered when the CTS line goes high
295 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
296 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
297 cbi(EIMSK, EIMSKB_CTS);
300 #endif // CONFIG_SER_HW_HANDSHAKE
304 * Serial 0 TX interrupt handler
306 SIGNAL(SIG_UART0_DATA)
308 if (fifo_isempty(&ser_handles[SER_UART0].txfifo))
310 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
312 * To avoid audio interference: always transmit useless char.
313 * Send the byte with the ninth bit cleared, the receiver in MCPM mode
317 UDR0 = SER_FILL_BYTE;
319 /* Disable UDR empty interrupt and transmitter */
320 UCSR0B = BV(RXCIE) | BV(RXEN);
323 #if defined(CONFIG_SER_HWHANDSHAKE)
326 // disable rx interrupt and tx, enable CTS interrupt
327 UCSR0B = BV(RXCIE) | BV(RXEN);
328 sbi(EIFR, EIMSKB_CTS);
329 sbi(EIMSK, EIMSKB_CTS);
331 #endif // CONFIG_SER_HWHANDSHAKE
334 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
335 /* Send with ninth bit set. Receiver in MCPM mode will receive it */
338 UDR0 = fifo_pop(&ser_handles[SER_UART0].txfifo);
346 * Serial 1 TX interrupt handler
348 SIGNAL(SIG_UART1_DATA)
350 if (fifo_isempty(&ser_handles[SER_UART1].txfifo))
352 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
354 * To avoid audio interference: always transmit useless char.
355 * Send the byte with the ninth bit cleared, the receiver in MCPM mode
359 UDR1 = SER_FILL_BYTE;
361 /* Disable UDR empty interrupt and transmitter */
362 UCSR1B = BV(RXCIE) | BV(RXEN);
365 #if defined(CONFIG_SER_HWHANDSHAKE)
368 // disable rx interrupt and tx, enable CTS interrupt
369 UCSR1B = BV(RXCIE) | BV(RXEN);
370 sbi(EIFR, EIMSKB_CTS);
371 sbi(EIMSK, EIMSKB_CTS);
373 #endif // CONFIG_SER_HWHANDSHAKE
376 #if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
377 /* Send with ninth bit set. Receiver in MCPM mode will receive it */
380 UDR1 = fifo_pop(&ser_handles[SER_UART1].txfifo);
383 #endif // AVR_HAS_UART1
387 * Serial 0 RX complete interrupt handler.
389 * This handler is interruptible.
390 * Interrupt are reenabled as soon as recv complete interrupt is
391 * disabled. Using INTERRUPT() is troublesome when the serial
392 * is heavily loaded, because an interrupt could be retriggered
393 * when executing the handler prologue before RXCIE is disabled.
395 SIGNAL(SIG_UART0_RECV)
397 /* Disable Recv complete IRQ */
398 UCSR0B &= ~BV(RXCIE);
401 /* Should be read before UDR */
402 ser_handles[SER_UART0].status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
404 /* To clear the RXC flag we must _always_ read the UDR even when we're
405 * not going to accept the incoming data, otherwise a new interrupt
406 * will occur once the handler terminates.
410 if (fifo_isfull(&ser_handles[SER_UART0].rxfifo))
411 ser_handles[SER_UART0].status |= SERRF_RXFIFOOVERRUN;
414 fifo_push(&ser_handles[SER_UART0].rxfifo, c);
415 #if defined(CONFIG_SER_HW_HANDSHAKE)
416 if (fifo_isfull(&ser_handles[SER_UART0].rxfifo))
420 /* Reenable receive complete int */
428 * Serial 1 RX complete interrupt handler.
430 * This handler is interruptible.
431 * Interrupt are reenabled as soon as recv complete interrupt is
432 * disabled. Using INTERRUPT() is troublesome when the serial
433 * is heavily loaded, because an interrupt could be retriggered
434 * when executing the handler prologue before RXCIE is disabled.
436 SIGNAL(SIG_UART1_RECV)
438 /* Disable Recv complete IRQ */
439 UCSR1B &= ~BV(RXCIE);
442 /* Should be read before UDR */
443 ser_handles[SER_UART1].status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
445 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
446 * not going to accept the incoming data
450 if (fifo_isfull(&ser_handles[SER_UART1].rxfifo))
451 ser_handles[SER_UART1].status |= SERRF_RXFIFOOVERRUN;
454 fifo_push(&ser_handles[SER_UART1].rxfifo, c);
455 #if defined(CONFIG_SER_HW_HANDSHAKE)
456 if (fifo_isfull(&ser_handles[SER_UART1].rxfifo))
460 /* Reenable receive complete int */
464 #endif // AVR_HAS_UART1
468 * SPI Flag: true if we are transmitting/receiving with the SPI.
470 * This kludge is necessary because the SPI sends and receives bytes
471 * at the same time and the SPI IRQ is unique for send/receive.
472 * The only way to start transmission is to write data in SPDR (this
473 * is done by spi_starttx()). We do this *only* if a transfer is
474 * not already started.
476 static volatile bool spi_sending = false;
478 static void spi_starttx(UNUSED(struct SerialHardware *, ctx))
482 DISABLE_IRQSAVE(flags);
484 /* Send data only if the SPI is not already transmitting */
485 if (!spi_sending && !fifo_isempty(&ser_handles[SER_SPI].txfifo))
487 SPDR = fifo_pop(&ser_handles[SER_SPI].txfifo);
491 ENABLE_IRQRESTORE(flags);
495 * SPI interrupt handler
499 /* Read incoming byte. */
500 if (!fifo_isfull(&ser_handles[SER_SPI].rxfifo))
501 fifo_push(&ser_handles[SER_SPI].rxfifo, SPDR);
505 ser_handles[SER_SPI].status |= SERRF_RXFIFOOVERRUN;
509 if (!fifo_isempty(&ser_handles[SER_SPI].txfifo))
510 SPDR = fifo_pop(&ser_handles[SER_SPI].txfifo);
516 static const struct SerialHardwareVT UART0_VT =
519 .cleanup = uart0_cleanup,
520 .setbaudrate = uart0_setbaudrate,
521 .setparity = uart0_setparity,
522 .enabletxirq = uart0_enabletxirq,
526 static const struct SerialHardwareVT UART1_VT =
529 .cleanup = uart1_cleanup,
530 .setbaudrate = uart1_setbaudrate,
531 .setparity = uart1_setparity,
532 .enabletxirq = uart1_enabletxirq,
534 #endif // AVR_HAS_UART1
536 static const struct SerialHardwareVT SPI_VT =
539 .cleanup = spi_cleanup,
540 .setbaudrate = spi_setbaudrate,
541 .setparity = spi_setparity,
542 .enabletxirq = spi_starttx,
545 static struct AvrSerial UARTDescs[SER_CNT] =
547 { .hw = { .table = &UART0_VT } },
549 { .hw = { .table = &UART1_VT } },
550 #endif // AVR_HAS_UART1
551 { .hw = { .table = &SPI_VT } },
554 struct SerialHardware* ser_hw_getdesc(int unit)
556 ASSERT(unit < SER_CNT);
557 return &UARTDescs[unit].hw;