4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 * Revision 1.10 2004/08/10 06:30:41 bernie
42 * Major redesign of serial bus policy handling.
44 * Revision 1.9 2004/08/02 20:20:29 aleph
45 * Merge from project_ks
47 * Revision 1.8 2004/07/29 22:57:09 bernie
48 * Several tweaks to reduce code size on ATmega8.
50 * Revision 1.7 2004/07/18 21:54:23 bernie
51 * Add ATmega8 support.
53 * Revision 1.5 2004/06/27 15:25:40 aleph
54 * Add missing callbacks for SPI;
55 * Change UNUSED() macro to new version with two args;
56 * Use TX line filling only on the correct KBUS serial port;
57 * Fix nasty IRQ disabling bug in recv complete hander for port 1.
59 * Revision 1.4 2004/06/03 11:27:09 bernie
60 * Add dual-license information.
62 * Revision 1.3 2004/06/02 21:35:24 aleph
63 * Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
65 * Revision 1.2 2004/05/23 18:21:53 bernie
66 * Trim CVS logs and cleanup header info.
75 #include <drv/timer.h>
76 #include <mware/fifobuf.h>
78 #include <avr/signal.h>
82 * \name Hardware handshake (RTS/CTS).
86 #define RTS_ON do {} while (0)
89 #define RTS_OFF do {} while (0)
92 #define IS_CTS_ON true
95 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
101 * \def CONFIG_SER_STROBE
103 * This is a debug facility that can be used to
104 * monitor SER interrupt activity on an external pin.
106 * To use strobes, redefine the macros SER_STROBE_ON,
107 * SER_STROBE_OFF and SER_STROBE_INIT and set
108 * CONFIG_SER_STROBE to 1.
110 #ifndef CONFIG_SER_STROBE
111 #define SER_STROBE_ON do {/*nop*/} while(0)
112 #define SER_STROBE_OFF do {/*nop*/} while(0)
113 #define SER_STROBE_INIT do {/*nop*/} while(0)
118 * \name Overridable serial hooks
120 * These can be redefined in hw.h to implement
121 * special bus policies such as half-duplex, 485, etc.
125 * TXBEGIN TXCHAR TXEND TXOFF
126 * | __________|__________ | |
129 * ______ __ __ __ __ __ __ ________________
130 * \/ \/ \/ \/ \/ \/ \/
131 * ______/\__/\__/\__/\__/\__/\__/
137 #ifndef SER_UART0_BUS_TXINIT
139 * Default TXINIT macro - invoked in uart0_init()
141 * - Enable both the receiver and the transmitter
142 * - Enable only the RX complete interrupt
144 #define SER_UART0_BUS_TXINIT do { \
145 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
149 #ifndef SER_UART0_BUS_TXBEGIN
151 * Invoked before starting a transmission
153 * - Enable both the receiver and the transmitter
154 * - Enable both the RX complete and UDR empty interrupts
156 #define SER_UART0_BUS_TXBEGIN do { \
157 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
161 #ifndef SER_UART0_BUS_TXCHAR
163 * Invoked to send one character.
165 #define SER_UART0_BUS_TXCHAR(c) do { \
170 #ifndef SER_UART0_BUS_TXEND
172 * Invoked as soon as the txfifo becomes empty
174 * - Keep both the receiver and the transmitter enabled
175 * - Keep the RX complete interrupt enabled
176 * - Disable the UDR empty interrupt
178 #define SER_UART0_BUS_TXEND do { \
179 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
183 #ifndef SER_UART0_BUS_TXOFF
185 * \def SER_UART0_BUS_TXOFF
187 * Invoked after the last character has been transmitted
189 * The default is no action.
193 #ifndef SER_UART1_BUS_TXINIT
194 /*! \sa SER_UART0_BUS_TXINIT */
195 #define SER_UART1_BUS_TXINIT do { \
196 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
199 #ifndef SER_UART1_BUS_TXBEGIN
200 /*! \sa SER_UART0_BUS_TXBEGIN */
201 #define SER_UART1_BUS_TXBEGIN do { \
202 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
205 #ifndef SER_UART1_BUS_TXCHAR
206 /*! \sa SER_UART0_BUS_TXCHAR */
207 #define SER_UART1_BUS_TXCHAR(c) do { \
211 #ifndef SER_UART1_BUS_TXEND
212 /*! \sa SER_UART0_BUS_TXEND */
213 #define SER_UART1_BUS_TXEND do { \
214 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
217 #ifndef SER_UART1_BUS_TXOFF
219 * \def SER_UART1_BUS_TXOFF
221 * \see SER_UART0_BUS_TXOFF
227 /* SPI port and pin configuration */
228 #define SPI_PORT PORTB
230 #define SPI_SCK_BIT PORTB1
231 #define SPI_MOSI_BIT PORTB2
232 #define SPI_MISO_BIT PORTB3
234 /* USART registers definitions */
235 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
236 #define AVR_HAS_UART1 1
237 #elif defined(__AVR_ATmega8__)
238 #define AVR_HAS_UART1 0
245 #define SIG_UART0_DATA SIG_UART_DATA
246 #define SIG_UART0_RECV SIG_UART_RECV
247 #elif defined(__AVR_ATmega103__)
248 #define AVR_HAS_UART1 0
253 #define SIG_UART0_DATA SIG_UART_DATA
254 #define SIG_UART0_RECV SIG_UART_RECV
256 #error Unknown architecture
260 /* From the high-level serial driver */
261 extern struct Serial ser_handles[SER_CNT];
264 * Internal hardware state structure
266 * \a sending var is true if we are transmitting.
267 * SPI note: this flag is necessary because the SPI sends and receives bytes
268 * at the same time and the SPI IRQ is unique for send/receive.
269 * The only way to start transmission is to write data in SPDR (this
270 * is done by spi_starttx()). We do this *only* if a transfer is
271 * not already started.
273 * For the USARTs the \a sending flag is useful for taking specific
274 * actions before sending a burst of data, at the start of a trasmission
275 * but not before every char sent.
279 struct SerialHardware hw;
280 volatile bool sending;
284 * These are to trick GCC into *not* using
285 * absolute addressing mode when accessing
286 * ser_handles, which is very expensive.
288 * Accessing through these pointers generates
289 * much shorter (and hopefully faster) code.
291 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
293 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
295 struct Serial *ser_spi = &ser_handles[SER_SPI];
302 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
304 SER_UART0_BUS_TXINIT;
308 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
313 static void uart0_enabletxirq(struct SerialHardware *_hw)
315 struct AvrSerial *hw = (struct AvrSerial *)_hw;
318 * WARNING: racy code here! The tx interrupt
319 * sets hw->sending to false when it runs with
320 * an empty fifo. The order of the statements
321 * in the if-block matters.
326 SER_UART0_BUS_TXBEGIN;
330 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
332 /* Compute baud-rate period */
333 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
335 #ifndef __AVR_ATmega103__
336 UBRR0H = (period) >> 8;
340 DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
343 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
345 #ifndef __AVR_ATmega103__
346 UCSR0C |= (parity) << UPM0;
352 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
354 SER_UART1_BUS_TXINIT;
359 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
364 static void uart1_enabletxirq(struct SerialHardware *_hw)
366 struct AvrSerial *hw = (struct AvrSerial *)_hw;
369 * WARNING: racy code here! The tx interrupt
370 * sets hw->sending to false when it runs with
371 * an empty fifo. The order of the statements
372 * in the if-block matters.
377 SER_UART1_BUS_TXBEGIN;
381 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
383 /* Compute baud-rate period */
384 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
386 UBRR1H = (period) >> 8;
389 DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
392 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
394 UCSR1C |= (parity) << UPM0;
397 #endif // AVR_HAS_UART1
399 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
402 * Set MOSI and SCK ports out, MISO in.
404 * The ATmega64/128 datasheet explicitly states that the input/output
405 * state of the SPI pins is not significant, as when the SPI is
406 * active the I/O port are overrided.
407 * This is *blatantly FALSE*.
409 * Moreover, the MISO pin on the board_kc *must* be in high impedance
410 * state even when the SPI is off, because the line is wired together
411 * with the KBus serial RX, and the transmitter of the slave boards
412 * would be unable to drive the line.
414 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
415 SPI_DDR &= ~BV(SPI_MISO_BIT);
416 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
417 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
420 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
423 /* Set all pins as inputs */
424 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
427 static void spi_starttx(struct SerialHardware *_hw)
429 struct AvrSerial *hw = (struct AvrSerial *)_hw;
432 DISABLE_IRQSAVE(flags);
434 /* Send data only if the SPI is not already transmitting */
435 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
438 SPDR = fifo_pop(&ser_spi->txfifo);
441 ENABLE_IRQRESTORE(flags);
444 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
449 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
457 * High-level interface data structures
459 static const struct SerialHardwareVT UART0_VT =
462 .cleanup = uart0_cleanup,
463 .setbaudrate = uart0_setbaudrate,
464 .setparity = uart0_setparity,
465 .enabletxirq = uart0_enabletxirq,
469 static const struct SerialHardwareVT UART1_VT =
472 .cleanup = uart1_cleanup,
473 .setbaudrate = uart1_setbaudrate,
474 .setparity = uart1_setparity,
475 .enabletxirq = uart1_enabletxirq,
477 #endif // AVR_HAS_UART1
479 static const struct SerialHardwareVT SPI_VT =
482 .cleanup = spi_cleanup,
483 .setbaudrate = spi_setbaudrate,
484 .setparity = spi_setparity,
485 .enabletxirq = spi_starttx,
488 static struct AvrSerial UARTDescs[SER_CNT] =
491 .hw = { .table = &UART0_VT },
496 .hw = { .table = &UART1_VT },
501 .hw = { .table = &SPI_VT },
506 struct SerialHardware* ser_hw_getdesc(int unit)
508 ASSERT(unit < SER_CNT);
509 return &UARTDescs[unit].hw;
518 #if CONFIG_SER_HWHANDSHAKE
520 //! This interrupt is triggered when the CTS line goes high
523 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
524 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
525 cbi(EIMSK, EIMSKB_CTS);
528 #endif // CONFIG_SER_HWHANDSHAKE
532 * Serial 0 TX interrupt handler
534 SIGNAL(SIG_UART0_DATA)
538 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
540 if (fifo_isempty(txfifo))
543 #ifndef SER_UART0_BUS_TXOFF
544 UARTDescs[SER_UART0].sending = false;
547 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
550 // Disable rx interrupt and tx, enable CTS interrupt
552 UCSR0B = BV(RXCIE) | BV(RXEN);
553 sbi(EIFR, EIMSKB_CTS);
554 sbi(EIMSK, EIMSKB_CTS);
559 char c = fifo_pop(txfifo);
560 SER_UART0_BUS_TXCHAR(c);
566 #ifdef SER_UART0_BUS_TXOFF
568 * Serial port 0 TX complete interrupt handler.
570 * This IRQ is usually disabled. The UDR-empty interrupt
571 * enables it when there's no more data to transmit.
572 * We need to wait until the last character has been
573 * transmitted before switching the 485 transceiver to
576 * The txfifo might have been refilled by putchar() while
577 * we were waiting for the transmission complete interrupt.
578 * In this case, we must restart the UDR empty interrupt,
579 * otherwise we'd stop the serial port with some data
580 * still pending in the buffer.
582 SIGNAL(SIG_UART0_TRANS)
586 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
587 if (fifo_isempty(txfifo))
590 UARTDescs[SER_UART0].sending = false;
593 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
597 #endif /* SER_UART0_BUS_TXOFF */
603 * Serial 1 TX interrupt handler
605 SIGNAL(SIG_UART1_DATA)
609 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
611 if (fifo_isempty(txfifo))
614 #ifndef SER_UART1_BUS_TXOFF
615 UARTDescs[SER_UART1].sending = false;
618 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
621 // Disable rx interrupt and tx, enable CTS interrupt
623 UCSR1B = BV(RXCIE) | BV(RXEN);
624 sbi(EIFR, EIMSKB_CTS);
625 sbi(EIMSK, EIMSKB_CTS);
630 char c = fifo_pop(txfifo);
631 SER_UART1_BUS_TXCHAR(c);
637 #ifdef SER_UART1_BUS_TXOFF
639 * Serial port 1 TX complete interrupt handler.
641 * \sa port 0 TX complete handler.
643 SIGNAL(SIG_UART1_TRANS)
647 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
648 if (fifo_isempty(txfifo))
651 UARTDescs[SER_UART1].sending = false;
654 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
658 #endif /* SER_UART1_BUS_TXOFF */
660 #endif // AVR_HAS_UART1
664 * Serial 0 RX complete interrupt handler.
666 * This handler is interruptible.
667 * Interrupt are reenabled as soon as recv complete interrupt is
668 * disabled. Using INTERRUPT() is troublesome when the serial
669 * is heavily loaded, because an interrupt could be retriggered
670 * when executing the handler prologue before RXCIE is disabled.
672 SIGNAL(SIG_UART0_RECV)
676 /* Disable Recv complete IRQ */
677 UCSR0B &= ~BV(RXCIE);
680 /* Should be read before UDR */
681 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
683 /* To clear the RXC flag we must _always_ read the UDR even when we're
684 * not going to accept the incoming data, otherwise a new interrupt
685 * will occur once the handler terminates.
688 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
690 if (fifo_isfull(rxfifo))
691 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
694 fifo_push(rxfifo, c);
695 #if CONFIG_SER_HWHANDSHAKE
696 if (fifo_isfull(rxfifo))
701 /* Reenable receive complete int */
711 * Serial 1 RX complete interrupt handler.
713 * This handler is interruptible.
714 * Interrupt are reenabled as soon as recv complete interrupt is
715 * disabled. Using INTERRUPT() is troublesome when the serial
716 * is heavily loaded, because an interrupt could be retriggered
717 * when executing the handler prologue before RXCIE is disabled.
719 SIGNAL(SIG_UART1_RECV)
723 /* Disable Recv complete IRQ */
724 UCSR1B &= ~BV(RXCIE);
727 /* Should be read before UDR */
728 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
730 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
731 * not going to accept the incoming data
734 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
736 if (fifo_isfull(rxfifo))
737 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
740 fifo_push(rxfifo, c);
741 #if CONFIG_SER_HWHANDSHAKE
742 if (fifo_isfull(rxfifo))
746 /* Reenable receive complete int */
752 #endif // AVR_HAS_UART1
756 * SPI interrupt handler
760 /* Read incoming byte. */
761 if (!fifo_isfull(&ser_spi->rxfifo))
762 fifo_push(&ser_spi->rxfifo, SPDR);
766 ser_spi->status |= SERRF_RXFIFOOVERRUN;
770 if (!fifo_isempty(&ser_spi->txfifo))
771 SPDR = fifo_pop(&ser_spi->txfifo);
773 UARTDescs[SER_SPI].sending = false;