4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.17 2004/10/19 07:52:35 bernie
42 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
44 *#* Revision 1.16 2004/10/03 18:45:48 bernie
45 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
47 *#* Revision 1.15 2004/09/14 21:05:36 bernie
48 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
50 *#* Revision 1.14 2004/09/06 21:50:00 bernie
53 *#* Revision 1.13 2004/09/06 21:40:50 bernie
54 *#* Move buffer handling in chip-specific driver.
56 *#* Revision 1.12 2004/08/29 22:06:10 bernie
57 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
59 *#* Revision 1.10 2004/08/10 06:30:41 bernie
60 *#* Major redesign of serial bus policy handling.
62 *#* Revision 1.9 2004/08/02 20:20:29 aleph
63 *#* Merge from project_ks
65 *#* Revision 1.8 2004/07/29 22:57:09 bernie
66 *#* Several tweaks to reduce code size on ATmega8.
68 *#* Revision 1.7 2004/07/18 21:54:23 bernie
69 *#* Add ATmega8 support.
71 *#* Revision 1.5 2004/06/27 15:25:40 aleph
72 *#* Add missing callbacks for SPI;
73 *#* Change UNUSED() macro to new version with two args;
74 *#* Use TX line filling only on the correct KBUS serial port;
75 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
77 *#* Revision 1.4 2004/06/03 11:27:09 bernie
78 *#* Add dual-license information.
80 *#* Revision 1.3 2004/06/02 21:35:24 aleph
81 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
83 *#* Revision 1.2 2004/05/23 18:21:53 bernie
84 *#* Trim CVS logs and cleanup header info.
91 #include "hw.h" /* Required for bus macros overrides */
94 #include <drv/timer.h>
95 #include <mware/fifobuf.h>
97 #include <avr/signal.h>
102 * \name Hardware handshake (RTS/CTS).
106 #define RTS_ON do {} while (0)
109 #define RTS_OFF do {} while (0)
112 #define IS_CTS_ON true
115 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
121 * \name Overridable serial bus hooks
123 * These can be redefined in hw.h to implement
124 * special bus policies such as half-duplex, 485, etc.
128 * TXBEGIN TXCHAR TXEND TXOFF
129 * | __________|__________ | |
132 * ______ __ __ __ __ __ __ ________________
133 * \/ \/ \/ \/ \/ \/ \/
134 * ______/\__/\__/\__/\__/\__/\__/
140 #ifndef SER_UART0_BUS_TXINIT
142 * Default TXINIT macro - invoked in uart0_init()
144 * - Enable both the receiver and the transmitter
145 * - Enable only the RX complete interrupt
147 #define SER_UART0_BUS_TXINIT do { \
148 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
152 #ifndef SER_UART0_BUS_TXBEGIN
154 * Invoked before starting a transmission
156 * - Enable both the receiver and the transmitter
157 * - Enable both the RX complete and UDR empty interrupts
159 #define SER_UART0_BUS_TXBEGIN do { \
160 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
164 #ifndef SER_UART0_BUS_TXCHAR
166 * Invoked to send one character.
168 #define SER_UART0_BUS_TXCHAR(c) do { \
173 #ifndef SER_UART0_BUS_TXEND
175 * Invoked as soon as the txfifo becomes empty
177 * - Keep both the receiver and the transmitter enabled
178 * - Keep the RX complete interrupt enabled
179 * - Disable the UDR empty interrupt
181 #define SER_UART0_BUS_TXEND do { \
182 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
186 #ifndef SER_UART0_BUS_TXOFF
188 * \def SER_UART0_BUS_TXOFF
190 * Invoked after the last character has been transmitted
192 * The default is no action.
196 #ifndef SER_UART1_BUS_TXINIT
197 /*! \sa SER_UART0_BUS_TXINIT */
198 #define SER_UART1_BUS_TXINIT do { \
199 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
202 #ifndef SER_UART1_BUS_TXBEGIN
203 /*! \sa SER_UART0_BUS_TXBEGIN */
204 #define SER_UART1_BUS_TXBEGIN do { \
205 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
208 #ifndef SER_UART1_BUS_TXCHAR
209 /*! \sa SER_UART0_BUS_TXCHAR */
210 #define SER_UART1_BUS_TXCHAR(c) do { \
214 #ifndef SER_UART1_BUS_TXEND
215 /*! \sa SER_UART0_BUS_TXEND */
216 #define SER_UART1_BUS_TXEND do { \
217 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
220 #ifndef SER_UART1_BUS_TXOFF
222 * \def SER_UART1_BUS_TXOFF
224 * \see SER_UART0_BUS_TXOFF
230 /* SPI port and pin configuration */
231 #define SPI_PORT PORTB
233 #define SPI_SCK_BIT PB1
234 #define SPI_MOSI_BIT PB2
235 #define SPI_MISO_BIT PB3
237 /* USART register definitions */
238 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
239 #define AVR_HAS_UART1 1
240 #elif CPU_AVR_ATMEGA8
241 #define AVR_HAS_UART1 0
248 #define SIG_UART0_DATA SIG_UART_DATA
249 #define SIG_UART0_RECV SIG_UART_RECV
250 #elif CPU_AVR_ATMEGA103
251 #define AVR_HAS_UART1 0
256 #define SIG_UART0_DATA SIG_UART_DATA
257 #define SIG_UART0_RECV SIG_UART_RECV
259 #error Unknown architecture
264 * \def CONFIG_SER_STROBE
266 * This is a debug facility that can be used to
267 * monitor SER interrupt activity on an external pin.
269 * To use strobes, redefine the macros SER_STROBE_ON,
270 * SER_STROBE_OFF and SER_STROBE_INIT and set
271 * CONFIG_SER_STROBE to 1.
273 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
274 #define SER_STROBE_ON do {/*nop*/} while(0)
275 #define SER_STROBE_OFF do {/*nop*/} while(0)
276 #define SER_STROBE_INIT do {/*nop*/} while(0)
280 /* From the high-level serial driver */
281 extern struct Serial ser_handles[SER_CNT];
283 /* TX and RX buffers */
284 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
285 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
287 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
288 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
290 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
291 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
295 * Internal hardware state structure
297 * The \a sending variable is true while the transmission
298 * interrupt is retriggering itself.
300 * For the USARTs the \a sending flag is useful for taking specific
301 * actions before sending a burst of data, at the start of a trasmission
302 * but not before every char sent.
304 * For the SPI, this flag is necessary because the SPI sends and receives
305 * bytes at the same time and the SPI IRQ is unique for send/receive.
306 * The only way to start transmission is to write data in SPDR (this
307 * is done by spi_starttx()). We do this *only* if a transfer is
308 * not already started.
312 struct SerialHardware hw;
313 volatile bool sending;
318 * These are to trick GCC into *not* using absolute addressing mode
319 * when accessing ser_handles, which is very expensive.
321 * Accessing through these pointers generates much shorter
322 * (and hopefully faster) code.
324 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
326 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
328 struct Serial *ser_spi = &ser_handles[SER_SPI];
335 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
337 SER_UART0_BUS_TXINIT;
341 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
346 static void uart0_enabletxirq(struct SerialHardware *_hw)
348 struct AvrSerial *hw = (struct AvrSerial *)_hw;
351 * WARNING: racy code here! The tx interrupt sets hw->sending to false
352 * when it runs with an empty fifo. The order of statements in the
358 SER_UART0_BUS_TXBEGIN;
362 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
364 /* Compute baud-rate period */
365 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
367 #ifndef __AVR_ATmega103__
368 UBRR0H = (period) >> 8;
372 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
375 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
377 #if !CPU_AVR_ATMEGA103
378 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
384 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
386 SER_UART1_BUS_TXINIT;
391 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
396 static void uart1_enabletxirq(struct SerialHardware *_hw)
398 struct AvrSerial *hw = (struct AvrSerial *)_hw;
401 * WARNING: racy code here! The tx interrupt
402 * sets hw->sending to false when it runs with
403 * an empty fifo. The order of the statements
404 * in the if-block matters.
409 SER_UART1_BUS_TXBEGIN;
413 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
415 /* Compute baud-rate period */
416 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
418 UBRR1H = (period) >> 8;
421 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
424 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
426 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
429 #endif // AVR_HAS_UART1
431 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
434 * Set MOSI and SCK ports out, MISO in.
436 * The ATmega64/128 datasheet explicitly states that the input/output
437 * state of the SPI pins is not significant, as when the SPI is
438 * active the I/O port are overrided.
439 * This is *blatantly FALSE*.
441 * Moreover, the MISO pin on the board_kc *must* be in high impedance
442 * state even when the SPI is off, because the line is wired together
443 * with the KBus serial RX, and the transmitter of the slave boards
444 * would be unable to drive the line.
446 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
447 SPI_DDR &= ~BV(SPI_MISO_BIT);
448 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
449 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
452 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
455 /* Set all pins as inputs */
456 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
459 static void spi_starttx(struct SerialHardware *_hw)
461 struct AvrSerial *hw = (struct AvrSerial *)_hw;
464 DISABLE_IRQSAVE(flags);
466 /* Send data only if the SPI is not already transmitting */
467 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
470 SPDR = fifo_pop(&ser_spi->txfifo);
473 ENABLE_IRQRESTORE(flags);
476 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
481 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
487 // FIXME: move into compiler.h? Ditch?
489 #define C99INIT(name,val) .name = val
490 #elif defined(__GNUC__)
491 #define C99INIT(name,val) name: val
493 #warning No designated initializers, double check your code
494 #define C99INIT(name,val) (val)
498 * High-level interface data structures
500 static const struct SerialHardwareVT UART0_VT =
502 C99INIT(init, uart0_init),
503 C99INIT(cleanup, uart0_cleanup),
504 C99INIT(setbaudrate, uart0_setbaudrate),
505 C99INIT(setparity, uart0_setparity),
506 C99INIT(enabletxirq, uart0_enabletxirq),
510 static const struct SerialHardwareVT UART1_VT =
512 C99INIT(init, uart1_init),
513 C99INIT(cleanup, uart1_cleanup),
514 C99INIT(setbaudrate, uart1_setbaudrate),
515 C99INIT(setparity, uart1_setparity),
516 C99INIT(enabletxirq, uart1_enabletxirq),
518 #endif // AVR_HAS_UART1
520 static const struct SerialHardwareVT SPI_VT =
522 C99INIT(init, spi_init),
523 C99INIT(cleanup, spi_cleanup),
524 C99INIT(setbaudrate, spi_setbaudrate),
525 C99INIT(setparity, spi_setparity),
526 C99INIT(enabletxirq, spi_starttx),
529 static struct AvrSerial UARTDescs[SER_CNT] =
533 C99INIT(table, &UART0_VT),
534 C99INIT(txbuffer, uart0_txbuffer),
535 C99INIT(rxbuffer, uart0_rxbuffer),
536 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
537 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
539 C99INIT(sending, false),
544 C99INIT(table, &UART1_VT),
545 C99INIT(txbuffer, uart1_txbuffer),
546 C99INIT(rxbuffer, uart1_rxbuffer),
547 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
548 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
550 C99INIT(sending, false),
555 C99INIT(table, &SPI_VT),
556 C99INIT(txbuffer, spi_txbuffer),
557 C99INIT(rxbuffer, spi_rxbuffer),
558 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
559 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
561 C99INIT(sending, false),
565 struct SerialHardware* ser_hw_getdesc(int unit)
567 ASSERT(unit < SER_CNT);
568 return &UARTDescs[unit].hw;
576 #if CONFIG_SER_HWHANDSHAKE
578 //! This interrupt is triggered when the CTS line goes high
581 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
582 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
583 cbi(EIMSK, EIMSKB_CTS);
586 #endif // CONFIG_SER_HWHANDSHAKE
590 * Serial 0 TX interrupt handler
592 SIGNAL(SIG_UART0_DATA)
596 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
598 if (fifo_isempty(txfifo))
601 #ifndef SER_UART0_BUS_TXOFF
602 UARTDescs[SER_UART0].sending = false;
605 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
608 // Disable rx interrupt and tx, enable CTS interrupt
610 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
611 sbi(EIFR, EIMSKB_CTS);
612 sbi(EIMSK, EIMSKB_CTS);
617 char c = fifo_pop(txfifo);
618 SER_UART0_BUS_TXCHAR(c);
624 #ifdef SER_UART0_BUS_TXOFF
626 * Serial port 0 TX complete interrupt handler.
628 * This IRQ is usually disabled. The UDR-empty interrupt
629 * enables it when there's no more data to transmit.
630 * We need to wait until the last character has been
631 * transmitted before switching the 485 transceiver to
634 * The txfifo might have been refilled by putchar() while
635 * we were waiting for the transmission complete interrupt.
636 * In this case, we must restart the UDR empty interrupt,
637 * otherwise we'd stop the serial port with some data
638 * still pending in the buffer.
640 SIGNAL(SIG_UART0_TRANS)
644 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
645 if (fifo_isempty(txfifo))
648 UARTDescs[SER_UART0].sending = false;
651 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
655 #endif /* SER_UART0_BUS_TXOFF */
661 * Serial 1 TX interrupt handler
663 SIGNAL(SIG_UART1_DATA)
667 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
669 if (fifo_isempty(txfifo))
672 #ifndef SER_UART1_BUS_TXOFF
673 UARTDescs[SER_UART1].sending = false;
676 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
679 // Disable rx interrupt and tx, enable CTS interrupt
681 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
682 sbi(EIFR, EIMSKB_CTS);
683 sbi(EIMSK, EIMSKB_CTS);
688 char c = fifo_pop(txfifo);
689 SER_UART1_BUS_TXCHAR(c);
695 #ifdef SER_UART1_BUS_TXOFF
697 * Serial port 1 TX complete interrupt handler.
699 * \sa port 0 TX complete handler.
701 SIGNAL(SIG_UART1_TRANS)
705 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
706 if (fifo_isempty(txfifo))
709 UARTDescs[SER_UART1].sending = false;
712 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
716 #endif /* SER_UART1_BUS_TXOFF */
718 #endif // AVR_HAS_UART1
722 * Serial 0 RX complete interrupt handler.
724 * This handler is interruptible.
725 * Interrupt are reenabled as soon as recv complete interrupt is
726 * disabled. Using INTERRUPT() is troublesome when the serial
727 * is heavily loaded, because an interrupt could be retriggered
728 * when executing the handler prologue before RXCIE is disabled.
730 * \note The code that re-enables interrupts is commented out
731 * because in some nasty cases the interrupt is retriggered.
732 * This is probably due to the RXC flag being set before
733 * RXCIE is cleared. Unfortunately the RXC flag is read-only
734 * and can't be cleared by code.
736 SIGNAL(SIG_UART0_RECV)
740 /* Disable Recv complete IRQ */
741 //UCSR0B &= ~BV(RXCIE);
744 /* Should be read before UDR */
745 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
747 /* To clear the RXC flag we must _always_ read the UDR even when we're
748 * not going to accept the incoming data, otherwise a new interrupt
749 * will occur once the handler terminates.
752 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
754 if (fifo_isfull(rxfifo))
755 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
758 fifo_push(rxfifo, c);
759 #if CONFIG_SER_HWHANDSHAKE
760 if (fifo_isfull(rxfifo))
765 /* Reenable receive complete int */
767 //UCSR0B |= BV(RXCIE);
776 * Serial 1 RX complete interrupt handler.
778 * This handler is interruptible.
779 * Interrupt are reenabled as soon as recv complete interrupt is
780 * disabled. Using INTERRUPT() is troublesome when the serial
781 * is heavily loaded, because an interrupt could be retriggered
782 * when executing the handler prologue before RXCIE is disabled.
784 * \see SIGNAL(SIG_UART0_RECV)
786 SIGNAL(SIG_UART1_RECV)
790 /* Disable Recv complete IRQ */
791 //UCSR1B &= ~BV(RXCIE);
794 /* Should be read before UDR */
795 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
797 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
798 * not going to accept the incoming data
801 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
802 //ASSERT_VALID_FIFO(rxfifo);
804 if (UNLIKELY(fifo_isfull(rxfifo)))
805 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
808 fifo_push(rxfifo, c);
809 #if CONFIG_SER_HWHANDSHAKE
810 if (fifo_isfull(rxfifo))
814 /* Re-enable receive complete int */
815 //UCSR1B |= BV(RXCIE);
820 #endif // AVR_HAS_UART1
824 * SPI interrupt handler
828 /* Read incoming byte. */
829 if (!fifo_isfull(&ser_spi->rxfifo))
830 fifo_push(&ser_spi->rxfifo, SPDR);
834 ser_spi->status |= SERRF_RXFIFOOVERRUN;
838 if (!fifo_isempty(&ser_spi->txfifo))
839 SPDR = fifo_pop(&ser_spi->txfifo);
841 UARTDescs[SER_SPI].sending = false;