4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.18 2004/12/08 08:03:48 bernie
44 *#* Revision 1.17 2004/10/19 07:52:35 bernie
45 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
47 *#* Revision 1.16 2004/10/03 18:45:48 bernie
48 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
50 *#* Revision 1.15 2004/09/14 21:05:36 bernie
51 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
53 *#* Revision 1.14 2004/09/06 21:50:00 bernie
56 *#* Revision 1.13 2004/09/06 21:40:50 bernie
57 *#* Move buffer handling in chip-specific driver.
59 *#* Revision 1.12 2004/08/29 22:06:10 bernie
60 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
62 *#* Revision 1.10 2004/08/10 06:30:41 bernie
63 *#* Major redesign of serial bus policy handling.
65 *#* Revision 1.9 2004/08/02 20:20:29 aleph
66 *#* Merge from project_ks
68 *#* Revision 1.8 2004/07/29 22:57:09 bernie
69 *#* Several tweaks to reduce code size on ATmega8.
71 *#* Revision 1.7 2004/07/18 21:54:23 bernie
72 *#* Add ATmega8 support.
74 *#* Revision 1.5 2004/06/27 15:25:40 aleph
75 *#* Add missing callbacks for SPI;
76 *#* Change UNUSED() macro to new version with two args;
77 *#* Use TX line filling only on the correct KBUS serial port;
78 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
80 *#* Revision 1.4 2004/06/03 11:27:09 bernie
81 *#* Add dual-license information.
83 *#* Revision 1.3 2004/06/02 21:35:24 aleph
84 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
86 *#* Revision 1.2 2004/05/23 18:21:53 bernie
87 *#* Trim CVS logs and cleanup header info.
94 #include "hw.h" /* Required for bus macros overrides */
97 #include <drv/timer.h>
98 #include <mware/fifobuf.h>
100 #include <avr/signal.h>
105 * \name Hardware handshake (RTS/CTS).
109 #define RTS_ON do {} while (0)
112 #define RTS_OFF do {} while (0)
115 #define IS_CTS_ON true
118 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
124 * \name Overridable serial bus hooks
126 * These can be redefined in hw.h to implement
127 * special bus policies such as half-duplex, 485, etc.
131 * TXBEGIN TXCHAR TXEND TXOFF
132 * | __________|__________ | |
135 * ______ __ __ __ __ __ __ ________________
136 * \/ \/ \/ \/ \/ \/ \/
137 * ______/\__/\__/\__/\__/\__/\__/
143 #ifndef SER_UART0_BUS_TXINIT
145 * Default TXINIT macro - invoked in uart0_init()
147 * - Enable both the receiver and the transmitter
148 * - Enable only the RX complete interrupt
150 #define SER_UART0_BUS_TXINIT do { \
151 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
155 #ifndef SER_UART0_BUS_TXBEGIN
157 * Invoked before starting a transmission
159 * - Enable both the receiver and the transmitter
160 * - Enable both the RX complete and UDR empty interrupts
162 #define SER_UART0_BUS_TXBEGIN do { \
163 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
167 #ifndef SER_UART0_BUS_TXCHAR
169 * Invoked to send one character.
171 #define SER_UART0_BUS_TXCHAR(c) do { \
176 #ifndef SER_UART0_BUS_TXEND
178 * Invoked as soon as the txfifo becomes empty
180 * - Keep both the receiver and the transmitter enabled
181 * - Keep the RX complete interrupt enabled
182 * - Disable the UDR empty interrupt
184 #define SER_UART0_BUS_TXEND do { \
185 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
189 #ifndef SER_UART0_BUS_TXOFF
191 * \def SER_UART0_BUS_TXOFF
193 * Invoked after the last character has been transmitted
195 * The default is no action.
198 #define SER_UART0_BUS_TXOFF
202 #ifndef SER_UART1_BUS_TXINIT
203 /*! \sa SER_UART0_BUS_TXINIT */
204 #define SER_UART1_BUS_TXINIT do { \
205 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
208 #ifndef SER_UART1_BUS_TXBEGIN
209 /*! \sa SER_UART0_BUS_TXBEGIN */
210 #define SER_UART1_BUS_TXBEGIN do { \
211 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
214 #ifndef SER_UART1_BUS_TXCHAR
215 /*! \sa SER_UART0_BUS_TXCHAR */
216 #define SER_UART1_BUS_TXCHAR(c) do { \
220 #ifndef SER_UART1_BUS_TXEND
221 /*! \sa SER_UART0_BUS_TXEND */
222 #define SER_UART1_BUS_TXEND do { \
223 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
226 #ifndef SER_UART1_BUS_TXOFF
228 * \def SER_UART1_BUS_TXOFF
230 * \see SER_UART0_BUS_TXOFF
233 #define SER_UART1_BUS_TXOFF
239 /* SPI port and pin configuration */
240 #define SPI_PORT PORTB
242 #define SPI_SCK_BIT PB1
243 #define SPI_MOSI_BIT PB2
244 #define SPI_MISO_BIT PB3
246 /* USART register definitions */
247 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
248 #define AVR_HAS_UART1 1
249 #elif CPU_AVR_ATMEGA8
250 #define AVR_HAS_UART1 0
257 #define SIG_UART0_DATA SIG_UART_DATA
258 #define SIG_UART0_RECV SIG_UART_RECV
259 #elif CPU_AVR_ATMEGA103
260 #define AVR_HAS_UART1 0
265 #define SIG_UART0_DATA SIG_UART_DATA
266 #define SIG_UART0_RECV SIG_UART_RECV
268 #error Unknown architecture
273 * \def CONFIG_SER_STROBE
275 * This is a debug facility that can be used to
276 * monitor SER interrupt activity on an external pin.
278 * To use strobes, redefine the macros SER_STROBE_ON,
279 * SER_STROBE_OFF and SER_STROBE_INIT and set
280 * CONFIG_SER_STROBE to 1.
282 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
283 #define SER_STROBE_ON do {/*nop*/} while(0)
284 #define SER_STROBE_OFF do {/*nop*/} while(0)
285 #define SER_STROBE_INIT do {/*nop*/} while(0)
289 /* From the high-level serial driver */
290 extern struct Serial ser_handles[SER_CNT];
292 /* TX and RX buffers */
293 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
294 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
296 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
297 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
299 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
300 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
304 * Internal hardware state structure
306 * The \a sending variable is true while the transmission
307 * interrupt is retriggering itself.
309 * For the USARTs the \a sending flag is useful for taking specific
310 * actions before sending a burst of data, at the start of a trasmission
311 * but not before every char sent.
313 * For the SPI, this flag is necessary because the SPI sends and receives
314 * bytes at the same time and the SPI IRQ is unique for send/receive.
315 * The only way to start transmission is to write data in SPDR (this
316 * is done by spi_starttx()). We do this *only* if a transfer is
317 * not already started.
321 struct SerialHardware hw;
322 volatile bool sending;
327 * These are to trick GCC into *not* using absolute addressing mode
328 * when accessing ser_handles, which is very expensive.
330 * Accessing through these pointers generates much shorter
331 * (and hopefully faster) code.
333 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
335 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
337 struct Serial *ser_spi = &ser_handles[SER_SPI];
344 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
346 SER_UART0_BUS_TXINIT;
350 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
355 static void uart0_enabletxirq(struct SerialHardware *_hw)
357 struct AvrSerial *hw = (struct AvrSerial *)_hw;
360 * WARNING: racy code here! The tx interrupt sets hw->sending to false
361 * when it runs with an empty fifo. The order of statements in the
367 SER_UART0_BUS_TXBEGIN;
371 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
373 /* Compute baud-rate period */
374 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
376 #ifndef __AVR_ATmega103__
377 UBRR0H = (period) >> 8;
381 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
384 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
386 #if !CPU_AVR_ATMEGA103
387 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
393 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
395 SER_UART1_BUS_TXINIT;
400 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
405 static void uart1_enabletxirq(struct SerialHardware *_hw)
407 struct AvrSerial *hw = (struct AvrSerial *)_hw;
410 * WARNING: racy code here! The tx interrupt
411 * sets hw->sending to false when it runs with
412 * an empty fifo. The order of the statements
413 * in the if-block matters.
418 SER_UART1_BUS_TXBEGIN;
422 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
424 /* Compute baud-rate period */
425 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
427 UBRR1H = (period) >> 8;
430 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
433 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
435 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
438 #endif // AVR_HAS_UART1
440 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
443 * Set MOSI and SCK ports out, MISO in.
445 * The ATmega64/128 datasheet explicitly states that the input/output
446 * state of the SPI pins is not significant, as when the SPI is
447 * active the I/O port are overrided.
448 * This is *blatantly FALSE*.
450 * Moreover, the MISO pin on the board_kc *must* be in high impedance
451 * state even when the SPI is off, because the line is wired together
452 * with the KBus serial RX, and the transmitter of the slave boards
453 * would be unable to drive the line.
455 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
456 SPI_DDR &= ~BV(SPI_MISO_BIT);
457 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
458 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
461 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
464 /* Set all pins as inputs */
465 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
468 static void spi_starttx(struct SerialHardware *_hw)
470 struct AvrSerial *hw = (struct AvrSerial *)_hw;
473 DISABLE_IRQSAVE(flags);
475 /* Send data only if the SPI is not already transmitting */
476 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
479 SPDR = fifo_pop(&ser_spi->txfifo);
482 ENABLE_IRQRESTORE(flags);
485 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
490 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
496 // FIXME: move into compiler.h? Ditch?
498 #define C99INIT(name,val) .name = val
499 #elif defined(__GNUC__)
500 #define C99INIT(name,val) name: val
502 #warning No designated initializers, double check your code
503 #define C99INIT(name,val) (val)
507 * High-level interface data structures
509 static const struct SerialHardwareVT UART0_VT =
511 C99INIT(init, uart0_init),
512 C99INIT(cleanup, uart0_cleanup),
513 C99INIT(setbaudrate, uart0_setbaudrate),
514 C99INIT(setparity, uart0_setparity),
515 C99INIT(enabletxirq, uart0_enabletxirq),
519 static const struct SerialHardwareVT UART1_VT =
521 C99INIT(init, uart1_init),
522 C99INIT(cleanup, uart1_cleanup),
523 C99INIT(setbaudrate, uart1_setbaudrate),
524 C99INIT(setparity, uart1_setparity),
525 C99INIT(enabletxirq, uart1_enabletxirq),
527 #endif // AVR_HAS_UART1
529 static const struct SerialHardwareVT SPI_VT =
531 C99INIT(init, spi_init),
532 C99INIT(cleanup, spi_cleanup),
533 C99INIT(setbaudrate, spi_setbaudrate),
534 C99INIT(setparity, spi_setparity),
535 C99INIT(enabletxirq, spi_starttx),
538 static struct AvrSerial UARTDescs[SER_CNT] =
542 C99INIT(table, &UART0_VT),
543 C99INIT(txbuffer, uart0_txbuffer),
544 C99INIT(rxbuffer, uart0_rxbuffer),
545 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
546 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
548 C99INIT(sending, false),
553 C99INIT(table, &UART1_VT),
554 C99INIT(txbuffer, uart1_txbuffer),
555 C99INIT(rxbuffer, uart1_rxbuffer),
556 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
557 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
559 C99INIT(sending, false),
564 C99INIT(table, &SPI_VT),
565 C99INIT(txbuffer, spi_txbuffer),
566 C99INIT(rxbuffer, spi_rxbuffer),
567 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
568 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
570 C99INIT(sending, false),
574 struct SerialHardware* ser_hw_getdesc(int unit)
576 ASSERT(unit < SER_CNT);
577 return &UARTDescs[unit].hw;
585 #if CONFIG_SER_HWHANDSHAKE
587 //! This interrupt is triggered when the CTS line goes high
590 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
591 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
592 cbi(EIMSK, EIMSKB_CTS);
595 #endif // CONFIG_SER_HWHANDSHAKE
599 * Serial 0 TX interrupt handler
601 SIGNAL(SIG_UART0_DATA)
605 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
607 if (fifo_isempty(txfifo))
610 #ifndef SER_UART0_BUS_TXOFF
611 UARTDescs[SER_UART0].sending = false;
614 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
617 // Disable rx interrupt and tx, enable CTS interrupt
619 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
620 sbi(EIFR, EIMSKB_CTS);
621 sbi(EIMSK, EIMSKB_CTS);
626 char c = fifo_pop(txfifo);
627 SER_UART0_BUS_TXCHAR(c);
633 #ifdef SER_UART0_BUS_TXOFF
635 * Serial port 0 TX complete interrupt handler.
637 * This IRQ is usually disabled. The UDR-empty interrupt
638 * enables it when there's no more data to transmit.
639 * We need to wait until the last character has been
640 * transmitted before switching the 485 transceiver to
643 * The txfifo might have been refilled by putchar() while
644 * we were waiting for the transmission complete interrupt.
645 * In this case, we must restart the UDR empty interrupt,
646 * otherwise we'd stop the serial port with some data
647 * still pending in the buffer.
649 SIGNAL(SIG_UART0_TRANS)
653 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
654 if (fifo_isempty(txfifo))
657 UARTDescs[SER_UART0].sending = false;
660 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
664 #endif /* SER_UART0_BUS_TXOFF */
670 * Serial 1 TX interrupt handler
672 SIGNAL(SIG_UART1_DATA)
676 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
678 if (fifo_isempty(txfifo))
681 #ifndef SER_UART1_BUS_TXOFF
682 UARTDescs[SER_UART1].sending = false;
685 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
688 // Disable rx interrupt and tx, enable CTS interrupt
690 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
691 sbi(EIFR, EIMSKB_CTS);
692 sbi(EIMSK, EIMSKB_CTS);
697 char c = fifo_pop(txfifo);
698 SER_UART1_BUS_TXCHAR(c);
704 #ifdef SER_UART1_BUS_TXOFF
706 * Serial port 1 TX complete interrupt handler.
708 * \sa port 0 TX complete handler.
710 SIGNAL(SIG_UART1_TRANS)
714 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
715 if (fifo_isempty(txfifo))
718 UARTDescs[SER_UART1].sending = false;
721 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
725 #endif /* SER_UART1_BUS_TXOFF */
727 #endif // AVR_HAS_UART1
731 * Serial 0 RX complete interrupt handler.
733 * This handler is interruptible.
734 * Interrupt are reenabled as soon as recv complete interrupt is
735 * disabled. Using INTERRUPT() is troublesome when the serial
736 * is heavily loaded, because an interrupt could be retriggered
737 * when executing the handler prologue before RXCIE is disabled.
739 * \note The code that re-enables interrupts is commented out
740 * because in some nasty cases the interrupt is retriggered.
741 * This is probably due to the RXC flag being set before
742 * RXCIE is cleared. Unfortunately the RXC flag is read-only
743 * and can't be cleared by code.
745 SIGNAL(SIG_UART0_RECV)
749 /* Disable Recv complete IRQ */
750 //UCSR0B &= ~BV(RXCIE);
753 /* Should be read before UDR */
754 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
756 /* To clear the RXC flag we must _always_ read the UDR even when we're
757 * not going to accept the incoming data, otherwise a new interrupt
758 * will occur once the handler terminates.
761 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
763 if (fifo_isfull(rxfifo))
764 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
767 fifo_push(rxfifo, c);
768 #if CONFIG_SER_HWHANDSHAKE
769 if (fifo_isfull(rxfifo))
774 /* Reenable receive complete int */
776 //UCSR0B |= BV(RXCIE);
785 * Serial 1 RX complete interrupt handler.
787 * This handler is interruptible.
788 * Interrupt are reenabled as soon as recv complete interrupt is
789 * disabled. Using INTERRUPT() is troublesome when the serial
790 * is heavily loaded, because an interrupt could be retriggered
791 * when executing the handler prologue before RXCIE is disabled.
793 * \see SIGNAL(SIG_UART0_RECV)
795 SIGNAL(SIG_UART1_RECV)
799 /* Disable Recv complete IRQ */
800 //UCSR1B &= ~BV(RXCIE);
803 /* Should be read before UDR */
804 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
806 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
807 * not going to accept the incoming data
810 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
811 //ASSERT_VALID_FIFO(rxfifo);
813 if (UNLIKELY(fifo_isfull(rxfifo)))
814 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
817 fifo_push(rxfifo, c);
818 #if CONFIG_SER_HWHANDSHAKE
819 if (fifo_isfull(rxfifo))
823 /* Re-enable receive complete int */
824 //UCSR1B |= BV(RXCIE);
829 #endif // AVR_HAS_UART1
833 * SPI interrupt handler
837 /* Read incoming byte. */
838 if (!fifo_isfull(&ser_spi->rxfifo))
839 fifo_push(&ser_spi->rxfifo, SPDR);
843 ser_spi->status |= SERRF_RXFIFOOVERRUN;
847 if (!fifo_isempty(&ser_spi->txfifo))
848 SPDR = fifo_pop(&ser_spi->txfifo);
850 UARTDescs[SER_SPI].sending = false;