4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.22 2004/12/31 17:47:45 bernie
42 *#* Rename UNUSED() to UNUSED_ARG().
44 *#* Revision 1.21 2004/12/13 12:07:06 bernie
45 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
47 *#* Revision 1.20 2004/12/13 11:51:43 bernie
48 *#* Fix a latent bug with reentrant serial IRQs.
50 *#* Revision 1.19 2004/12/13 11:51:08 bernie
51 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
53 *#* Revision 1.18 2004/12/08 08:03:48 bernie
56 *#* Revision 1.17 2004/10/19 07:52:35 bernie
57 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
59 *#* Revision 1.16 2004/10/03 18:45:48 bernie
60 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
62 *#* Revision 1.15 2004/09/14 21:05:36 bernie
63 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
65 *#* Revision 1.14 2004/09/06 21:50:00 bernie
68 *#* Revision 1.13 2004/09/06 21:40:50 bernie
69 *#* Move buffer handling in chip-specific driver.
71 *#* Revision 1.12 2004/08/29 22:06:10 bernie
72 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
74 *#* Revision 1.10 2004/08/10 06:30:41 bernie
75 *#* Major redesign of serial bus policy handling.
77 *#* Revision 1.9 2004/08/02 20:20:29 aleph
78 *#* Merge from project_ks
80 *#* Revision 1.8 2004/07/29 22:57:09 bernie
81 *#* Several tweaks to reduce code size on ATmega8.
83 *#* Revision 1.7 2004/07/18 21:54:23 bernie
84 *#* Add ATmega8 support.
86 *#* Revision 1.5 2004/06/27 15:25:40 aleph
87 *#* Add missing callbacks for SPI;
88 *#* Change UNUSED() macro to new version with two args;
89 *#* Use TX line filling only on the correct KBUS serial port;
90 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
92 *#* Revision 1.4 2004/06/03 11:27:09 bernie
93 *#* Add dual-license information.
95 *#* Revision 1.3 2004/06/02 21:35:24 aleph
96 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
98 *#* Revision 1.2 2004/05/23 18:21:53 bernie
99 *#* Trim CVS logs and cleanup header info.
106 #include "hw.h" /* Required for bus macros overrides */
109 #include <drv/timer.h>
110 #include <mware/fifobuf.h>
112 #include <avr/signal.h>
117 * \name Hardware handshake (RTS/CTS).
121 #define RTS_ON do {} while (0)
124 #define RTS_OFF do {} while (0)
127 #define IS_CTS_ON true
130 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
136 * \name Overridable serial bus hooks
138 * These can be redefined in hw.h to implement
139 * special bus policies such as half-duplex, 485, etc.
143 * TXBEGIN TXCHAR TXEND TXOFF
144 * | __________|__________ | |
147 * ______ __ __ __ __ __ __ ________________
148 * \/ \/ \/ \/ \/ \/ \/
149 * ______/\__/\__/\__/\__/\__/\__/
155 #ifndef SER_UART0_BUS_TXINIT
157 * Default TXINIT macro - invoked in uart0_init()
159 * - Enable both the receiver and the transmitter
160 * - Enable only the RX complete interrupt
162 #define SER_UART0_BUS_TXINIT do { \
163 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
167 #ifndef SER_UART0_BUS_TXBEGIN
169 * Invoked before starting a transmission
171 * - Enable both the receiver and the transmitter
172 * - Enable both the RX complete and UDR empty interrupts
174 #define SER_UART0_BUS_TXBEGIN do { \
175 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
179 #ifndef SER_UART0_BUS_TXCHAR
181 * Invoked to send one character.
183 #define SER_UART0_BUS_TXCHAR(c) do { \
188 #ifndef SER_UART0_BUS_TXEND
190 * Invoked as soon as the txfifo becomes empty
192 * - Keep both the receiver and the transmitter enabled
193 * - Keep the RX complete interrupt enabled
194 * - Disable the UDR empty interrupt
196 #define SER_UART0_BUS_TXEND do { \
197 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
201 #ifndef SER_UART0_BUS_TXOFF
203 * \def SER_UART0_BUS_TXOFF
205 * Invoked after the last character has been transmitted
207 * The default is no action.
210 #define SER_UART0_BUS_TXOFF
214 #ifndef SER_UART1_BUS_TXINIT
215 /*! \sa SER_UART0_BUS_TXINIT */
216 #define SER_UART1_BUS_TXINIT do { \
217 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
220 #ifndef SER_UART1_BUS_TXBEGIN
221 /*! \sa SER_UART0_BUS_TXBEGIN */
222 #define SER_UART1_BUS_TXBEGIN do { \
223 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
226 #ifndef SER_UART1_BUS_TXCHAR
227 /*! \sa SER_UART0_BUS_TXCHAR */
228 #define SER_UART1_BUS_TXCHAR(c) do { \
232 #ifndef SER_UART1_BUS_TXEND
233 /*! \sa SER_UART0_BUS_TXEND */
234 #define SER_UART1_BUS_TXEND do { \
235 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
238 #ifndef SER_UART1_BUS_TXOFF
240 * \def SER_UART1_BUS_TXOFF
242 * \see SER_UART0_BUS_TXOFF
245 #define SER_UART1_BUS_TXOFF
251 /* SPI port and pin configuration */
252 #define SPI_PORT PORTB
254 #define SPI_SCK_BIT PB1
255 #define SPI_MOSI_BIT PB2
256 #define SPI_MISO_BIT PB3
258 /* USART register definitions */
259 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
260 #define AVR_HAS_UART1 1
261 #elif CPU_AVR_ATMEGA8
262 #define AVR_HAS_UART1 0
269 #define SIG_UART0_DATA SIG_UART_DATA
270 #define SIG_UART0_RECV SIG_UART_RECV
271 #elif CPU_AVR_ATMEGA103
272 #define AVR_HAS_UART1 0
277 #define SIG_UART0_DATA SIG_UART_DATA
278 #define SIG_UART0_RECV SIG_UART_RECV
280 #error Unknown architecture
285 * \def CONFIG_SER_STROBE
287 * This is a debug facility that can be used to
288 * monitor SER interrupt activity on an external pin.
290 * To use strobes, redefine the macros SER_STROBE_ON,
291 * SER_STROBE_OFF and SER_STROBE_INIT and set
292 * CONFIG_SER_STROBE to 1.
294 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
295 #define SER_STROBE_ON do {/*nop*/} while(0)
296 #define SER_STROBE_OFF do {/*nop*/} while(0)
297 #define SER_STROBE_INIT do {/*nop*/} while(0)
301 /* From the high-level serial driver */
302 extern struct Serial ser_handles[SER_CNT];
304 /* TX and RX buffers */
305 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
306 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
308 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
309 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
311 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
312 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
316 * Internal hardware state structure
318 * The \a sending variable is true while the transmission
319 * interrupt is retriggering itself.
321 * For the USARTs the \a sending flag is useful for taking specific
322 * actions before sending a burst of data, at the start of a trasmission
323 * but not before every char sent.
325 * For the SPI, this flag is necessary because the SPI sends and receives
326 * bytes at the same time and the SPI IRQ is unique for send/receive.
327 * The only way to start transmission is to write data in SPDR (this
328 * is done by spi_starttx()). We do this *only* if a transfer is
329 * not already started.
333 struct SerialHardware hw;
334 volatile bool sending;
339 * These are to trick GCC into *not* using absolute addressing mode
340 * when accessing ser_handles, which is very expensive.
342 * Accessing through these pointers generates much shorter
343 * (and hopefully faster) code.
345 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
347 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
349 struct Serial *ser_spi = &ser_handles[SER_SPI];
356 static void uart0_init(
357 UNUSED_ARG(struct SerialHardware *, _hw),
358 UNUSED_ARG(struct Serial *, ser))
360 SER_UART0_BUS_TXINIT;
364 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
369 static void uart0_enabletxirq(struct SerialHardware *_hw)
371 struct AvrSerial *hw = (struct AvrSerial *)_hw;
374 * WARNING: racy code here! The tx interrupt sets hw->sending to false
375 * when it runs with an empty fifo. The order of statements in the
381 SER_UART0_BUS_TXBEGIN;
385 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
387 /* Compute baud-rate period */
388 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
390 #ifndef __AVR_ATmega103__
391 UBRR0H = (period) >> 8;
395 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
398 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
400 #if !CPU_AVR_ATMEGA103
401 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
407 static void uart1_init(
408 UNUSED_ARG(struct SerialHardware *, _hw),
409 UNUSED_ARG(struct Serial *, ser))
411 SER_UART1_BUS_TXINIT;
416 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
421 static void uart1_enabletxirq(struct SerialHardware *_hw)
423 struct AvrSerial *hw = (struct AvrSerial *)_hw;
426 * WARNING: racy code here! The tx interrupt
427 * sets hw->sending to false when it runs with
428 * an empty fifo. The order of the statements
429 * in the if-block matters.
434 SER_UART1_BUS_TXBEGIN;
438 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
440 /* Compute baud-rate period */
441 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
443 UBRR1H = (period) >> 8;
446 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
449 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
451 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
454 #endif // AVR_HAS_UART1
456 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
459 * Set MOSI and SCK ports out, MISO in.
461 * The ATmega64/128 datasheet explicitly states that the input/output
462 * state of the SPI pins is not significant, as when the SPI is
463 * active the I/O port are overrided.
464 * This is *blatantly FALSE*.
466 * Moreover, the MISO pin on the board_kc *must* be in high impedance
467 * state even when the SPI is off, because the line is wired together
468 * with the KBus serial RX, and the transmitter of the slave boards
469 * would be unable to drive the line.
471 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
472 SPI_DDR &= ~BV(SPI_MISO_BIT);
473 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
474 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
477 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
480 /* Set all pins as inputs */
481 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
484 static void spi_starttx(struct SerialHardware *_hw)
486 struct AvrSerial *hw = (struct AvrSerial *)_hw;
489 IRQ_SAVE_DISABLE(flags);
491 /* Send data only if the SPI is not already transmitting */
492 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
495 SPDR = fifo_pop(&ser_spi->txfifo);
501 static void spi_setbaudrate(
502 UNUSED_ARG(struct SerialHardware *, _hw),
503 UNUSED_ARG(unsigned long, rate))
508 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
514 // FIXME: move into compiler.h? Ditch?
516 #define C99INIT(name,val) .name = val
517 #elif defined(__GNUC__)
518 #define C99INIT(name,val) name: val
520 #warning No designated initializers, double check your code
521 #define C99INIT(name,val) (val)
525 * High-level interface data structures
527 static const struct SerialHardwareVT UART0_VT =
529 C99INIT(init, uart0_init),
530 C99INIT(cleanup, uart0_cleanup),
531 C99INIT(setbaudrate, uart0_setbaudrate),
532 C99INIT(setparity, uart0_setparity),
533 C99INIT(enabletxirq, uart0_enabletxirq),
537 static const struct SerialHardwareVT UART1_VT =
539 C99INIT(init, uart1_init),
540 C99INIT(cleanup, uart1_cleanup),
541 C99INIT(setbaudrate, uart1_setbaudrate),
542 C99INIT(setparity, uart1_setparity),
543 C99INIT(enabletxirq, uart1_enabletxirq),
545 #endif // AVR_HAS_UART1
547 static const struct SerialHardwareVT SPI_VT =
549 C99INIT(init, spi_init),
550 C99INIT(cleanup, spi_cleanup),
551 C99INIT(setbaudrate, spi_setbaudrate),
552 C99INIT(setparity, spi_setparity),
553 C99INIT(enabletxirq, spi_starttx),
556 static struct AvrSerial UARTDescs[SER_CNT] =
560 C99INIT(table, &UART0_VT),
561 C99INIT(txbuffer, uart0_txbuffer),
562 C99INIT(rxbuffer, uart0_rxbuffer),
563 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
564 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
566 C99INIT(sending, false),
571 C99INIT(table, &UART1_VT),
572 C99INIT(txbuffer, uart1_txbuffer),
573 C99INIT(rxbuffer, uart1_rxbuffer),
574 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
575 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
577 C99INIT(sending, false),
582 C99INIT(table, &SPI_VT),
583 C99INIT(txbuffer, spi_txbuffer),
584 C99INIT(rxbuffer, spi_rxbuffer),
585 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
586 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
588 C99INIT(sending, false),
592 struct SerialHardware* ser_hw_getdesc(int unit)
594 ASSERT(unit < SER_CNT);
595 return &UARTDescs[unit].hw;
603 #if CONFIG_SER_HWHANDSHAKE
605 //! This interrupt is triggered when the CTS line goes high
608 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
609 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
610 cbi(EIMSK, EIMSKB_CTS);
613 #endif // CONFIG_SER_HWHANDSHAKE
617 * Serial 0 TX interrupt handler
619 SIGNAL(SIG_UART0_DATA)
623 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
625 if (fifo_isempty(txfifo))
628 #ifndef SER_UART0_BUS_TXOFF
629 UARTDescs[SER_UART0].sending = false;
632 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
635 // Disable rx interrupt and tx, enable CTS interrupt
637 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
638 sbi(EIFR, EIMSKB_CTS);
639 sbi(EIMSK, EIMSKB_CTS);
644 char c = fifo_pop(txfifo);
645 SER_UART0_BUS_TXCHAR(c);
651 #ifdef SER_UART0_BUS_TXOFF
653 * Serial port 0 TX complete interrupt handler.
655 * This IRQ is usually disabled. The UDR-empty interrupt
656 * enables it when there's no more data to transmit.
657 * We need to wait until the last character has been
658 * transmitted before switching the 485 transceiver to
661 * The txfifo might have been refilled by putchar() while
662 * we were waiting for the transmission complete interrupt.
663 * In this case, we must restart the UDR empty interrupt,
664 * otherwise we'd stop the serial port with some data
665 * still pending in the buffer.
667 SIGNAL(SIG_UART0_TRANS)
671 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
672 if (fifo_isempty(txfifo))
675 UARTDescs[SER_UART0].sending = false;
678 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
682 #endif /* SER_UART0_BUS_TXOFF */
688 * Serial 1 TX interrupt handler
690 SIGNAL(SIG_UART1_DATA)
694 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
696 if (fifo_isempty(txfifo))
699 #ifndef SER_UART1_BUS_TXOFF
700 UARTDescs[SER_UART1].sending = false;
703 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
706 // Disable rx interrupt and tx, enable CTS interrupt
708 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
709 sbi(EIFR, EIMSKB_CTS);
710 sbi(EIMSK, EIMSKB_CTS);
715 char c = fifo_pop(txfifo);
716 SER_UART1_BUS_TXCHAR(c);
722 #ifdef SER_UART1_BUS_TXOFF
724 * Serial port 1 TX complete interrupt handler.
726 * \sa port 0 TX complete handler.
728 SIGNAL(SIG_UART1_TRANS)
732 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
733 if (fifo_isempty(txfifo))
736 UARTDescs[SER_UART1].sending = false;
739 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
743 #endif /* SER_UART1_BUS_TXOFF */
745 #endif // AVR_HAS_UART1
749 * Serial 0 RX complete interrupt handler.
751 * This handler is interruptible.
752 * Interrupt are reenabled as soon as recv complete interrupt is
753 * disabled. Using INTERRUPT() is troublesome when the serial
754 * is heavily loaded, because an interrupt could be retriggered
755 * when executing the handler prologue before RXCIE is disabled.
757 * \note The code that re-enables interrupts is commented out
758 * because in some nasty cases the interrupt is retriggered.
759 * This is probably due to the RXC flag being set before
760 * RXCIE is cleared. Unfortunately the RXC flag is read-only
761 * and can't be cleared by code.
763 SIGNAL(SIG_UART0_RECV)
767 /* Disable Recv complete IRQ */
768 //UCSR0B &= ~BV(RXCIE);
771 /* Should be read before UDR */
772 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
774 /* To clear the RXC flag we must _always_ read the UDR even when we're
775 * not going to accept the incoming data, otherwise a new interrupt
776 * will occur once the handler terminates.
779 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
781 if (fifo_isfull(rxfifo))
782 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
785 fifo_push(rxfifo, c);
786 #if CONFIG_SER_HWHANDSHAKE
787 if (fifo_isfull(rxfifo))
792 /* Reenable receive complete int */
794 //UCSR0B |= BV(RXCIE);
803 * Serial 1 RX complete interrupt handler.
805 * This handler is interruptible.
806 * Interrupt are reenabled as soon as recv complete interrupt is
807 * disabled. Using INTERRUPT() is troublesome when the serial
808 * is heavily loaded, because an interrupt could be retriggered
809 * when executing the handler prologue before RXCIE is disabled.
811 * \see SIGNAL(SIG_UART0_RECV)
813 SIGNAL(SIG_UART1_RECV)
817 /* Disable Recv complete IRQ */
818 //UCSR1B &= ~BV(RXCIE);
821 /* Should be read before UDR */
822 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
824 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
825 * not going to accept the incoming data
828 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
829 //ASSERT_VALID_FIFO(rxfifo);
831 if (UNLIKELY(fifo_isfull(rxfifo)))
832 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
835 fifo_push(rxfifo, c);
836 #if CONFIG_SER_HWHANDSHAKE
837 if (fifo_isfull(rxfifo))
841 /* Re-enable receive complete int */
843 //UCSR1B |= BV(RXCIE);
848 #endif // AVR_HAS_UART1
852 * SPI interrupt handler
856 /* Read incoming byte. */
857 if (!fifo_isfull(&ser_spi->rxfifo))
858 fifo_push(&ser_spi->rxfifo, SPDR);
862 ser_spi->status |= SERRF_RXFIFOOVERRUN;
866 if (!fifo_isempty(&ser_spi->txfifo))
867 SPDR = fifo_pop(&ser_spi->txfifo);
869 UARTDescs[SER_SPI].sending = false;