4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.24 2005/01/14 00:49:16 aleph
42 *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
44 *#* Revision 1.23 2005/01/11 18:09:07 aleph
45 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
47 *#* Revision 1.22 2004/12/31 17:47:45 bernie
48 *#* Rename UNUSED() to UNUSED_ARG().
50 *#* Revision 1.21 2004/12/13 12:07:06 bernie
51 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
53 *#* Revision 1.20 2004/12/13 11:51:43 bernie
54 *#* Fix a latent bug with reentrant serial IRQs.
56 *#* Revision 1.19 2004/12/13 11:51:08 bernie
57 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
59 *#* Revision 1.18 2004/12/08 08:03:48 bernie
62 *#* Revision 1.17 2004/10/19 07:52:35 bernie
63 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
65 *#* Revision 1.16 2004/10/03 18:45:48 bernie
66 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
68 *#* Revision 1.15 2004/09/14 21:05:36 bernie
69 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
71 *#* Revision 1.14 2004/09/06 21:50:00 bernie
74 *#* Revision 1.13 2004/09/06 21:40:50 bernie
75 *#* Move buffer handling in chip-specific driver.
77 *#* Revision 1.12 2004/08/29 22:06:10 bernie
78 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
80 *#* Revision 1.10 2004/08/10 06:30:41 bernie
81 *#* Major redesign of serial bus policy handling.
83 *#* Revision 1.9 2004/08/02 20:20:29 aleph
84 *#* Merge from project_ks
86 *#* Revision 1.8 2004/07/29 22:57:09 bernie
87 *#* Several tweaks to reduce code size on ATmega8.
89 *#* Revision 1.7 2004/07/18 21:54:23 bernie
90 *#* Add ATmega8 support.
92 *#* Revision 1.5 2004/06/27 15:25:40 aleph
93 *#* Add missing callbacks for SPI;
94 *#* Change UNUSED() macro to new version with two args;
95 *#* Use TX line filling only on the correct KBUS serial port;
96 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
98 *#* Revision 1.4 2004/06/03 11:27:09 bernie
99 *#* Add dual-license information.
101 *#* Revision 1.3 2004/06/02 21:35:24 aleph
102 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
104 *#* Revision 1.2 2004/05/23 18:21:53 bernie
105 *#* Trim CVS logs and cleanup header info.
112 #include "hw.h" /* Required for bus macros overrides */
115 #include <drv/timer.h>
116 #include <mware/fifobuf.h>
118 #include <avr/signal.h>
123 * \name Hardware handshake (RTS/CTS).
127 #define RTS_ON do {} while (0)
130 #define RTS_OFF do {} while (0)
133 #define IS_CTS_ON true
136 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
142 * \name Overridable serial bus hooks
144 * These can be redefined in hw.h to implement
145 * special bus policies such as half-duplex, 485, etc.
149 * TXBEGIN TXCHAR TXEND TXOFF
150 * | __________|__________ | |
153 * ______ __ __ __ __ __ __ ________________
154 * \/ \/ \/ \/ \/ \/ \/
155 * ______/\__/\__/\__/\__/\__/\__/
161 #ifndef SER_UART0_BUS_TXINIT
163 * Default TXINIT macro - invoked in uart0_init()
165 * - Enable both the receiver and the transmitter
166 * - Enable only the RX complete interrupt
168 #define SER_UART0_BUS_TXINIT do { \
169 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
173 #ifndef SER_UART0_BUS_TXBEGIN
175 * Invoked before starting a transmission
177 * - Enable both the receiver and the transmitter
178 * - Enable both the RX complete and UDR empty interrupts
180 #define SER_UART0_BUS_TXBEGIN do { \
181 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
185 #ifndef SER_UART0_BUS_TXCHAR
187 * Invoked to send one character.
189 #define SER_UART0_BUS_TXCHAR(c) do { \
194 #ifndef SER_UART0_BUS_TXEND
196 * Invoked as soon as the txfifo becomes empty
198 * - Keep both the receiver and the transmitter enabled
199 * - Keep the RX complete interrupt enabled
200 * - Disable the UDR empty interrupt
202 #define SER_UART0_BUS_TXEND do { \
203 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
207 #ifndef SER_UART0_BUS_TXOFF
209 * \def SER_UART0_BUS_TXOFF
211 * Invoked after the last character has been transmitted
213 * The default is no action.
216 #define SER_UART0_BUS_TXOFF
220 #ifndef SER_UART1_BUS_TXINIT
221 /*! \sa SER_UART0_BUS_TXINIT */
222 #define SER_UART1_BUS_TXINIT do { \
223 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
226 #ifndef SER_UART1_BUS_TXBEGIN
227 /*! \sa SER_UART0_BUS_TXBEGIN */
228 #define SER_UART1_BUS_TXBEGIN do { \
229 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
232 #ifndef SER_UART1_BUS_TXCHAR
233 /*! \sa SER_UART0_BUS_TXCHAR */
234 #define SER_UART1_BUS_TXCHAR(c) do { \
238 #ifndef SER_UART1_BUS_TXEND
239 /*! \sa SER_UART0_BUS_TXEND */
240 #define SER_UART1_BUS_TXEND do { \
241 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
244 #ifndef SER_UART1_BUS_TXOFF
246 * \def SER_UART1_BUS_TXOFF
248 * \see SER_UART0_BUS_TXOFF
251 #define SER_UART1_BUS_TXOFF
258 * \name Overridable SPI hooks
260 * These can be redefined in hw.h to implement
261 * special bus policies such as slave select pin handling, etc.
265 #ifndef SER_SPI_BUS_TXINIT
267 * \def SER_SPI_BUS_TXINIT
269 * Default TXINIT macro - invoked in spi_init()
270 * The default is no action.
272 #define SER_SPI_BUS_TXINIT
275 #ifndef SER_SPI_BUS_TXCLOSE
277 * \def SER_SPI_BUS_TXCLOSE
279 * Invoked after the last character has been transmitted.
280 * The default is no action.
282 #define SER_SPI_BUS_TXCLOSE
287 /* SPI port and pin configuration */
288 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
289 #define SPI_PORT PORTB
291 #define SPI_SCK_BIT PB1
292 #define SPI_MOSI_BIT PB2
293 #define SPI_MISO_BIT PB3
294 #elif CPU_AVR_ATMEGA8
295 #define SPI_PORT PORTB
297 #define SPI_SCK_BIT PB5
298 #define SPI_MOSI_BIT PB3
299 #define SPI_MISO_BIT PB4
301 #error Unknown architecture
304 /* USART register definitions */
305 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
306 #define AVR_HAS_UART1 1
307 #elif CPU_AVR_ATMEGA8
308 #define AVR_HAS_UART1 0
315 #define SIG_UART0_DATA SIG_UART_DATA
316 #define SIG_UART0_RECV SIG_UART_RECV
317 #define SIG_UART0_TRANS SIG_UART_TRANS
318 #elif CPU_AVR_ATMEGA103
319 #define AVR_HAS_UART1 0
324 #define SIG_UART0_DATA SIG_UART_DATA
325 #define SIG_UART0_RECV SIG_UART_RECV
326 #define SIG_UART0_TRANS SIG_UART_TRANS
328 #error Unknown architecture
333 * \def CONFIG_SER_STROBE
335 * This is a debug facility that can be used to
336 * monitor SER interrupt activity on an external pin.
338 * To use strobes, redefine the macros SER_STROBE_ON,
339 * SER_STROBE_OFF and SER_STROBE_INIT and set
340 * CONFIG_SER_STROBE to 1.
342 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
343 #define SER_STROBE_ON do {/*nop*/} while(0)
344 #define SER_STROBE_OFF do {/*nop*/} while(0)
345 #define SER_STROBE_INIT do {/*nop*/} while(0)
349 /* From the high-level serial driver */
350 extern struct Serial ser_handles[SER_CNT];
352 /* TX and RX buffers */
353 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
354 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
356 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
357 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
359 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
360 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
364 * Internal hardware state structure
366 * The \a sending variable is true while the transmission
367 * interrupt is retriggering itself.
369 * For the USARTs the \a sending flag is useful for taking specific
370 * actions before sending a burst of data, at the start of a trasmission
371 * but not before every char sent.
373 * For the SPI, this flag is necessary because the SPI sends and receives
374 * bytes at the same time and the SPI IRQ is unique for send/receive.
375 * The only way to start transmission is to write data in SPDR (this
376 * is done by spi_starttx()). We do this *only* if a transfer is
377 * not already started.
381 struct SerialHardware hw;
382 volatile bool sending;
387 * These are to trick GCC into *not* using absolute addressing mode
388 * when accessing ser_handles, which is very expensive.
390 * Accessing through these pointers generates much shorter
391 * (and hopefully faster) code.
393 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
395 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
397 struct Serial *ser_spi = &ser_handles[SER_SPI];
404 static void uart0_init(
405 UNUSED_ARG(struct SerialHardware *, _hw),
406 UNUSED_ARG(struct Serial *, ser))
408 SER_UART0_BUS_TXINIT;
413 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
418 static void uart0_enabletxirq(struct SerialHardware *_hw)
420 struct AvrSerial *hw = (struct AvrSerial *)_hw;
423 * WARNING: racy code here! The tx interrupt sets hw->sending to false
424 * when it runs with an empty fifo. The order of statements in the
430 SER_UART0_BUS_TXBEGIN;
434 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
436 /* Compute baud-rate period */
437 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
439 #ifndef __AVR_ATmega103__
440 UBRR0H = (period) >> 8;
444 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
447 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
449 #if !CPU_AVR_ATMEGA103
450 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
456 static void uart1_init(
457 UNUSED_ARG(struct SerialHardware *, _hw),
458 UNUSED_ARG(struct Serial *, ser))
460 SER_UART1_BUS_TXINIT;
465 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
470 static void uart1_enabletxirq(struct SerialHardware *_hw)
472 struct AvrSerial *hw = (struct AvrSerial *)_hw;
475 * WARNING: racy code here! The tx interrupt
476 * sets hw->sending to false when it runs with
477 * an empty fifo. The order of the statements
478 * in the if-block matters.
483 SER_UART1_BUS_TXBEGIN;
487 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
489 /* Compute baud-rate period */
490 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
492 UBRR1H = (period) >> 8;
495 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
498 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
500 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
503 #endif // AVR_HAS_UART1
505 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
508 * Set MOSI and SCK ports out, MISO in.
510 * The ATmega64/128 datasheet explicitly states that the input/output
511 * state of the SPI pins is not significant, as when the SPI is
512 * active the I/O port are overrided.
513 * This is *blatantly FALSE*.
515 * Moreover, the MISO pin on the board_kc *must* be in high impedance
516 * state even when the SPI is off, because the line is wired together
517 * with the KBus serial RX, and the transmitter of the slave boards
518 * would be unable to drive the line.
520 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
521 SPI_DDR &= ~BV(SPI_MISO_BIT);
522 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
523 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
530 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
536 /* Set all pins as inputs */
537 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
540 static void spi_starttx(struct SerialHardware *_hw)
542 struct AvrSerial *hw = (struct AvrSerial *)_hw;
545 IRQ_SAVE_DISABLE(flags);
547 /* Send data only if the SPI is not already transmitting */
548 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
551 SPDR = fifo_pop(&ser_spi->txfifo);
557 static void spi_setbaudrate(
558 UNUSED_ARG(struct SerialHardware *, _hw),
559 UNUSED_ARG(unsigned long, rate))
564 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
569 static bool tx_sending(struct SerialHardware* _hw)
571 struct AvrSerial *hw = (struct AvrSerial *)_hw;
577 // FIXME: move into compiler.h? Ditch?
579 #define C99INIT(name,val) .name = val
580 #elif defined(__GNUC__)
581 #define C99INIT(name,val) name: val
583 #warning No designated initializers, double check your code
584 #define C99INIT(name,val) (val)
588 * High-level interface data structures
590 static const struct SerialHardwareVT UART0_VT =
592 C99INIT(init, uart0_init),
593 C99INIT(cleanup, uart0_cleanup),
594 C99INIT(setBaudrate, uart0_setbaudrate),
595 C99INIT(setParity, uart0_setparity),
596 C99INIT(txStart, uart0_enabletxirq),
597 C99INIT(txSending, tx_sending),
601 static const struct SerialHardwareVT UART1_VT =
603 C99INIT(init, uart1_init),
604 C99INIT(cleanup, uart1_cleanup),
605 C99INIT(setBaudrate, uart1_setbaudrate),
606 C99INIT(setParity, uart1_setparity),
607 C99INIT(txStart, uart1_enabletxirq),
608 C99INIT(txSending, tx_sending),
610 #endif // AVR_HAS_UART1
612 static const struct SerialHardwareVT SPI_VT =
614 C99INIT(init, spi_init),
615 C99INIT(cleanup, spi_cleanup),
616 C99INIT(setBaudrate, spi_setbaudrate),
617 C99INIT(setParity, spi_setparity),
618 C99INIT(txStart, spi_starttx),
619 C99INIT(txSending, tx_sending),
622 static struct AvrSerial UARTDescs[SER_CNT] =
626 C99INIT(table, &UART0_VT),
627 C99INIT(txbuffer, uart0_txbuffer),
628 C99INIT(rxbuffer, uart0_rxbuffer),
629 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
630 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
632 C99INIT(sending, false),
637 C99INIT(table, &UART1_VT),
638 C99INIT(txbuffer, uart1_txbuffer),
639 C99INIT(rxbuffer, uart1_rxbuffer),
640 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
641 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
643 C99INIT(sending, false),
648 C99INIT(table, &SPI_VT),
649 C99INIT(txbuffer, spi_txbuffer),
650 C99INIT(rxbuffer, spi_rxbuffer),
651 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
652 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
654 C99INIT(sending, false),
658 struct SerialHardware* ser_hw_getdesc(int unit)
660 ASSERT(unit < SER_CNT);
661 return &UARTDescs[unit].hw;
669 #if CONFIG_SER_HWHANDSHAKE
671 //! This interrupt is triggered when the CTS line goes high
674 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
675 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
676 cbi(EIMSK, EIMSKB_CTS);
679 #endif // CONFIG_SER_HWHANDSHAKE
683 * Serial 0 TX interrupt handler
685 SIGNAL(SIG_UART0_DATA)
689 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
691 if (fifo_isempty(txfifo))
694 #ifndef SER_UART0_BUS_TXOFF
695 UARTDescs[SER_UART0].sending = false;
698 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
701 // Disable rx interrupt and tx, enable CTS interrupt
703 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
704 sbi(EIFR, EIMSKB_CTS);
705 sbi(EIMSK, EIMSKB_CTS);
710 char c = fifo_pop(txfifo);
711 SER_UART0_BUS_TXCHAR(c);
717 #ifdef SER_UART0_BUS_TXOFF
719 * Serial port 0 TX complete interrupt handler.
721 * This IRQ is usually disabled. The UDR-empty interrupt
722 * enables it when there's no more data to transmit.
723 * We need to wait until the last character has been
724 * transmitted before switching the 485 transceiver to
727 * The txfifo might have been refilled by putchar() while
728 * we were waiting for the transmission complete interrupt.
729 * In this case, we must restart the UDR empty interrupt,
730 * otherwise we'd stop the serial port with some data
731 * still pending in the buffer.
733 SIGNAL(SIG_UART0_TRANS)
737 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
738 if (fifo_isempty(txfifo))
741 UARTDescs[SER_UART0].sending = false;
744 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
748 #endif /* SER_UART0_BUS_TXOFF */
754 * Serial 1 TX interrupt handler
756 SIGNAL(SIG_UART1_DATA)
760 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
762 if (fifo_isempty(txfifo))
765 #ifndef SER_UART1_BUS_TXOFF
766 UARTDescs[SER_UART1].sending = false;
769 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
772 // Disable rx interrupt and tx, enable CTS interrupt
774 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
775 sbi(EIFR, EIMSKB_CTS);
776 sbi(EIMSK, EIMSKB_CTS);
781 char c = fifo_pop(txfifo);
782 SER_UART1_BUS_TXCHAR(c);
788 #ifdef SER_UART1_BUS_TXOFF
790 * Serial port 1 TX complete interrupt handler.
792 * \sa port 0 TX complete handler.
794 SIGNAL(SIG_UART1_TRANS)
798 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
799 if (fifo_isempty(txfifo))
802 UARTDescs[SER_UART1].sending = false;
805 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
809 #endif /* SER_UART1_BUS_TXOFF */
811 #endif // AVR_HAS_UART1
815 * Serial 0 RX complete interrupt handler.
817 * This handler is interruptible.
818 * Interrupt are reenabled as soon as recv complete interrupt is
819 * disabled. Using INTERRUPT() is troublesome when the serial
820 * is heavily loaded, because an interrupt could be retriggered
821 * when executing the handler prologue before RXCIE is disabled.
823 * \note The code that re-enables interrupts is commented out
824 * because in some nasty cases the interrupt is retriggered.
825 * This is probably due to the RXC flag being set before
826 * RXCIE is cleared. Unfortunately the RXC flag is read-only
827 * and can't be cleared by code.
829 SIGNAL(SIG_UART0_RECV)
833 /* Disable Recv complete IRQ */
834 //UCSR0B &= ~BV(RXCIE);
837 /* Should be read before UDR */
838 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
840 /* To clear the RXC flag we must _always_ read the UDR even when we're
841 * not going to accept the incoming data, otherwise a new interrupt
842 * will occur once the handler terminates.
845 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
847 if (fifo_isfull(rxfifo))
848 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
851 fifo_push(rxfifo, c);
852 #if CONFIG_SER_HWHANDSHAKE
853 if (fifo_isfull(rxfifo))
858 /* Reenable receive complete int */
860 //UCSR0B |= BV(RXCIE);
869 * Serial 1 RX complete interrupt handler.
871 * This handler is interruptible.
872 * Interrupt are reenabled as soon as recv complete interrupt is
873 * disabled. Using INTERRUPT() is troublesome when the serial
874 * is heavily loaded, because an interrupt could be retriggered
875 * when executing the handler prologue before RXCIE is disabled.
877 * \see SIGNAL(SIG_UART0_RECV)
879 SIGNAL(SIG_UART1_RECV)
883 /* Disable Recv complete IRQ */
884 //UCSR1B &= ~BV(RXCIE);
887 /* Should be read before UDR */
888 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
890 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
891 * not going to accept the incoming data
894 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
895 //ASSERT_VALID_FIFO(rxfifo);
897 if (UNLIKELY(fifo_isfull(rxfifo)))
898 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
901 fifo_push(rxfifo, c);
902 #if CONFIG_SER_HWHANDSHAKE
903 if (fifo_isfull(rxfifo))
907 /* Re-enable receive complete int */
909 //UCSR1B |= BV(RXCIE);
914 #endif // AVR_HAS_UART1
918 * SPI interrupt handler
924 /* Read incoming byte. */
925 if (!fifo_isfull(&ser_spi->rxfifo))
926 fifo_push(&ser_spi->rxfifo, SPDR);
930 ser_spi->status |= SERRF_RXFIFOOVERRUN;
934 if (!fifo_isempty(&ser_spi->txfifo))
935 SPDR = fifo_pop(&ser_spi->txfifo);
937 UARTDescs[SER_SPI].sending = false;