4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.27 2005/07/03 15:19:31 bernie
44 *#* Revision 1.26 2005/04/11 19:10:27 bernie
45 *#* Include top-level headers from cfg/ subdir.
47 *#* Revision 1.25 2005/01/25 08:37:26 bernie
48 *#* CONFIG_SER_HWHANDSHAKE fixes.
50 *#* Revision 1.24 2005/01/14 00:49:16 aleph
51 *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
53 *#* Revision 1.23 2005/01/11 18:09:07 aleph
54 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
56 *#* Revision 1.22 2004/12/31 17:47:45 bernie
57 *#* Rename UNUSED() to UNUSED_ARG().
59 *#* Revision 1.21 2004/12/13 12:07:06 bernie
60 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
62 *#* Revision 1.20 2004/12/13 11:51:43 bernie
63 *#* Fix a latent bug with reentrant serial IRQs.
65 *#* Revision 1.19 2004/12/13 11:51:08 bernie
66 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
68 *#* Revision 1.18 2004/12/08 08:03:48 bernie
71 *#* Revision 1.17 2004/10/19 07:52:35 bernie
72 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
74 *#* Revision 1.16 2004/10/03 18:45:48 bernie
75 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
77 *#* Revision 1.15 2004/09/14 21:05:36 bernie
78 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
80 *#* Revision 1.14 2004/09/06 21:50:00 bernie
83 *#* Revision 1.13 2004/09/06 21:40:50 bernie
84 *#* Move buffer handling in chip-specific driver.
86 *#* Revision 1.12 2004/08/29 22:06:10 bernie
87 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
89 *#* Revision 1.10 2004/08/10 06:30:41 bernie
90 *#* Major redesign of serial bus policy handling.
92 *#* Revision 1.9 2004/08/02 20:20:29 aleph
93 *#* Merge from project_ks
95 *#* Revision 1.8 2004/07/29 22:57:09 bernie
96 *#* Several tweaks to reduce code size on ATmega8.
98 *#* Revision 1.7 2004/07/18 21:54:23 bernie
99 *#* Add ATmega8 support.
101 *#* Revision 1.5 2004/06/27 15:25:40 aleph
102 *#* Add missing callbacks for SPI;
103 *#* Change UNUSED() macro to new version with two args;
104 *#* Use TX line filling only on the correct KBUS serial port;
105 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
107 *#* Revision 1.4 2004/06/03 11:27:09 bernie
108 *#* Add dual-license information.
110 *#* Revision 1.3 2004/06/02 21:35:24 aleph
111 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
113 *#* Revision 1.2 2004/05/23 18:21:53 bernie
114 *#* Trim CVS logs and cleanup header info.
120 #include <cfg/config.h>
121 #include "hw.h" /* Required for bus macros overrides */
123 #include <cfg/debug.h>
124 #include <drv/timer.h>
125 #include <mware/fifobuf.h>
127 #include <avr/signal.h>
131 #if !CONFIG_SER_HWHANDSHAKE
133 * \name Hardware handshake (RTS/CTS).
136 #define RTS_ON do {} while (0)
137 #define RTS_OFF do {} while (0)
138 #define IS_CTS_ON true
139 #define EIMSKF_CTS 0 /*!< Dummy value, must be overridden */
145 * \name Overridable serial bus hooks
147 * These can be redefined in hw.h to implement
148 * special bus policies such as half-duplex, 485, etc.
152 * TXBEGIN TXCHAR TXEND TXOFF
153 * | __________|__________ | |
156 * ______ __ __ __ __ __ __ ________________
157 * \/ \/ \/ \/ \/ \/ \/
158 * ______/\__/\__/\__/\__/\__/\__/
164 #ifndef SER_UART0_BUS_TXINIT
166 * Default TXINIT macro - invoked in uart0_init()
168 * - Enable both the receiver and the transmitter
169 * - Enable only the RX complete interrupt
171 #define SER_UART0_BUS_TXINIT do { \
172 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
176 #ifndef SER_UART0_BUS_TXBEGIN
178 * Invoked before starting a transmission
180 * - Enable both the receiver and the transmitter
181 * - Enable both the RX complete and UDR empty interrupts
183 #define SER_UART0_BUS_TXBEGIN do { \
184 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
188 #ifndef SER_UART0_BUS_TXCHAR
190 * Invoked to send one character.
192 #define SER_UART0_BUS_TXCHAR(c) do { \
197 #ifndef SER_UART0_BUS_TXEND
199 * Invoked as soon as the txfifo becomes empty
201 * - Keep both the receiver and the transmitter enabled
202 * - Keep the RX complete interrupt enabled
203 * - Disable the UDR empty interrupt
205 #define SER_UART0_BUS_TXEND do { \
206 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
210 #ifndef SER_UART0_BUS_TXOFF
212 * \def SER_UART0_BUS_TXOFF
214 * Invoked after the last character has been transmitted
216 * The default is no action.
219 #define SER_UART0_BUS_TXOFF
223 #ifndef SER_UART1_BUS_TXINIT
224 /*! \sa SER_UART0_BUS_TXINIT */
225 #define SER_UART1_BUS_TXINIT do { \
226 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
229 #ifndef SER_UART1_BUS_TXBEGIN
230 /*! \sa SER_UART0_BUS_TXBEGIN */
231 #define SER_UART1_BUS_TXBEGIN do { \
232 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
235 #ifndef SER_UART1_BUS_TXCHAR
236 /*! \sa SER_UART0_BUS_TXCHAR */
237 #define SER_UART1_BUS_TXCHAR(c) do { \
241 #ifndef SER_UART1_BUS_TXEND
242 /*! \sa SER_UART0_BUS_TXEND */
243 #define SER_UART1_BUS_TXEND do { \
244 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
247 #ifndef SER_UART1_BUS_TXOFF
249 * \def SER_UART1_BUS_TXOFF
251 * \see SER_UART0_BUS_TXOFF
254 #define SER_UART1_BUS_TXOFF
261 * \name Overridable SPI hooks
263 * These can be redefined in hw.h to implement
264 * special bus policies such as slave select pin handling, etc.
268 #ifndef SER_SPI_BUS_TXINIT
270 * Default TXINIT macro - invoked in spi_init()
271 * The default is no action.
273 #define SER_SPI_BUS_TXINIT
276 #ifndef SER_SPI_BUS_TXCLOSE
278 * Invoked after the last character has been transmitted.
279 * The default is no action.
281 #define SER_SPI_BUS_TXCLOSE
286 /* SPI port and pin configuration */
287 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
288 #define SPI_PORT PORTB
290 #define SPI_SCK_BIT PB1
291 #define SPI_MOSI_BIT PB2
292 #define SPI_MISO_BIT PB3
293 #elif CPU_AVR_ATMEGA8
294 #define SPI_PORT PORTB
296 #define SPI_SCK_BIT PB5
297 #define SPI_MOSI_BIT PB3
298 #define SPI_MISO_BIT PB4
300 #error Unknown architecture
303 /* USART register definitions */
304 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
305 #define AVR_HAS_UART1 1
306 #elif CPU_AVR_ATMEGA8
307 #define AVR_HAS_UART1 0
314 #define SIG_UART0_DATA SIG_UART_DATA
315 #define SIG_UART0_RECV SIG_UART_RECV
316 #define SIG_UART0_TRANS SIG_UART_TRANS
317 #elif CPU_AVR_ATMEGA103
318 #define AVR_HAS_UART1 0
323 #define SIG_UART0_DATA SIG_UART_DATA
324 #define SIG_UART0_RECV SIG_UART_RECV
325 #define SIG_UART0_TRANS SIG_UART_TRANS
327 #error Unknown architecture
332 * \def CONFIG_SER_STROBE
334 * This is a debug facility that can be used to
335 * monitor SER interrupt activity on an external pin.
337 * To use strobes, redefine the macros SER_STROBE_ON,
338 * SER_STROBE_OFF and SER_STROBE_INIT and set
339 * CONFIG_SER_STROBE to 1.
341 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
342 #define SER_STROBE_ON do {/*nop*/} while(0)
343 #define SER_STROBE_OFF do {/*nop*/} while(0)
344 #define SER_STROBE_INIT do {/*nop*/} while(0)
348 /* From the high-level serial driver */
349 extern struct Serial ser_handles[SER_CNT];
351 /* TX and RX buffers */
352 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
353 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
355 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
356 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
358 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
359 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
363 * Internal hardware state structure
365 * The \a sending variable is true while the transmission
366 * interrupt is retriggering itself.
368 * For the USARTs the \a sending flag is useful for taking specific
369 * actions before sending a burst of data, at the start of a trasmission
370 * but not before every char sent.
372 * For the SPI, this flag is necessary because the SPI sends and receives
373 * bytes at the same time and the SPI IRQ is unique for send/receive.
374 * The only way to start transmission is to write data in SPDR (this
375 * is done by spi_starttx()). We do this *only* if a transfer is
376 * not already started.
380 struct SerialHardware hw;
381 volatile bool sending;
386 * These are to trick GCC into *not* using absolute addressing mode
387 * when accessing ser_handles, which is very expensive.
389 * Accessing through these pointers generates much shorter
390 * (and hopefully faster) code.
392 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
394 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
396 struct Serial *ser_spi = &ser_handles[SER_SPI];
403 static void uart0_init(
404 UNUSED_ARG(struct SerialHardware *, _hw),
405 UNUSED_ARG(struct Serial *, ser))
407 SER_UART0_BUS_TXINIT;
412 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
417 static void uart0_enabletxirq(struct SerialHardware *_hw)
419 struct AvrSerial *hw = (struct AvrSerial *)_hw;
422 * WARNING: racy code here! The tx interrupt sets hw->sending to false
423 * when it runs with an empty fifo. The order of statements in the
429 SER_UART0_BUS_TXBEGIN;
433 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
435 /* Compute baud-rate period */
436 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
438 #if !CPU_AVR_ATMEGA103
439 UBRR0H = (period) >> 8;
443 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
446 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
448 #if !CPU_AVR_ATMEGA103
449 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
455 static void uart1_init(
456 UNUSED_ARG(struct SerialHardware *, _hw),
457 UNUSED_ARG(struct Serial *, ser))
459 SER_UART1_BUS_TXINIT;
464 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
469 static void uart1_enabletxirq(struct SerialHardware *_hw)
471 struct AvrSerial *hw = (struct AvrSerial *)_hw;
474 * WARNING: racy code here! The tx interrupt
475 * sets hw->sending to false when it runs with
476 * an empty fifo. The order of the statements
477 * in the if-block matters.
482 SER_UART1_BUS_TXBEGIN;
486 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
488 /* Compute baud-rate period */
489 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
491 UBRR1H = (period) >> 8;
494 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
497 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
499 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
502 #endif // AVR_HAS_UART1
504 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
507 * Set MOSI and SCK ports out, MISO in.
509 * The ATmega64/128 datasheet explicitly states that the input/output
510 * state of the SPI pins is not significant, as when the SPI is
511 * active the I/O port are overrided.
512 * This is *blatantly FALSE*.
514 * Moreover, the MISO pin on the board_kc *must* be in high impedance
515 * state even when the SPI is off, because the line is wired together
516 * with the KBus serial RX, and the transmitter of the slave boards
517 * would be unable to drive the line.
519 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
520 SPI_DDR &= ~BV(SPI_MISO_BIT);
521 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
522 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
529 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
535 /* Set all pins as inputs */
536 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
539 static void spi_starttx(struct SerialHardware *_hw)
541 struct AvrSerial *hw = (struct AvrSerial *)_hw;
544 IRQ_SAVE_DISABLE(flags);
546 /* Send data only if the SPI is not already transmitting */
547 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
550 SPDR = fifo_pop(&ser_spi->txfifo);
556 static void spi_setbaudrate(
557 UNUSED_ARG(struct SerialHardware *, _hw),
558 UNUSED_ARG(unsigned long, rate))
563 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
568 static bool tx_sending(struct SerialHardware* _hw)
570 struct AvrSerial *hw = (struct AvrSerial *)_hw;
576 // FIXME: move into compiler.h? Ditch?
578 #define C99INIT(name,val) .name = val
579 #elif defined(__GNUC__)
580 #define C99INIT(name,val) name: val
582 #warning No designated initializers, double check your code
583 #define C99INIT(name,val) (val)
587 * High-level interface data structures
589 static const struct SerialHardwareVT UART0_VT =
591 C99INIT(init, uart0_init),
592 C99INIT(cleanup, uart0_cleanup),
593 C99INIT(setBaudrate, uart0_setbaudrate),
594 C99INIT(setParity, uart0_setparity),
595 C99INIT(txStart, uart0_enabletxirq),
596 C99INIT(txSending, tx_sending),
600 static const struct SerialHardwareVT UART1_VT =
602 C99INIT(init, uart1_init),
603 C99INIT(cleanup, uart1_cleanup),
604 C99INIT(setBaudrate, uart1_setbaudrate),
605 C99INIT(setParity, uart1_setparity),
606 C99INIT(txStart, uart1_enabletxirq),
607 C99INIT(txSending, tx_sending),
609 #endif // AVR_HAS_UART1
611 static const struct SerialHardwareVT SPI_VT =
613 C99INIT(init, spi_init),
614 C99INIT(cleanup, spi_cleanup),
615 C99INIT(setBaudrate, spi_setbaudrate),
616 C99INIT(setParity, spi_setparity),
617 C99INIT(txStart, spi_starttx),
618 C99INIT(txSending, tx_sending),
621 static struct AvrSerial UARTDescs[SER_CNT] =
625 C99INIT(table, &UART0_VT),
626 C99INIT(txbuffer, uart0_txbuffer),
627 C99INIT(rxbuffer, uart0_rxbuffer),
628 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
629 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
631 C99INIT(sending, false),
636 C99INIT(table, &UART1_VT),
637 C99INIT(txbuffer, uart1_txbuffer),
638 C99INIT(rxbuffer, uart1_rxbuffer),
639 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
640 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
642 C99INIT(sending, false),
647 C99INIT(table, &SPI_VT),
648 C99INIT(txbuffer, spi_txbuffer),
649 C99INIT(rxbuffer, spi_rxbuffer),
650 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
651 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
653 C99INIT(sending, false),
657 struct SerialHardware* ser_hw_getdesc(int unit)
659 ASSERT(unit < SER_CNT);
660 return &UARTDescs[unit].hw;
668 #if CONFIG_SER_HWHANDSHAKE
670 //! This interrupt is triggered when the CTS line goes high
673 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
674 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
675 EIMSK &= ~EIMSKF_CTS;
678 #endif // CONFIG_SER_HWHANDSHAKE
682 * Serial 0 TX interrupt handler
684 SIGNAL(SIG_UART0_DATA)
688 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
690 if (fifo_isempty(txfifo))
693 #ifndef SER_UART0_BUS_TXOFF
694 UARTDescs[SER_UART0].sending = false;
697 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
700 // Disable rx interrupt and tx, enable CTS interrupt
702 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
709 char c = fifo_pop(txfifo);
710 SER_UART0_BUS_TXCHAR(c);
716 #ifdef SER_UART0_BUS_TXOFF
718 * Serial port 0 TX complete interrupt handler.
720 * This IRQ is usually disabled. The UDR-empty interrupt
721 * enables it when there's no more data to transmit.
722 * We need to wait until the last character has been
723 * transmitted before switching the 485 transceiver to
726 * The txfifo might have been refilled by putchar() while
727 * we were waiting for the transmission complete interrupt.
728 * In this case, we must restart the UDR empty interrupt,
729 * otherwise we'd stop the serial port with some data
730 * still pending in the buffer.
732 SIGNAL(SIG_UART0_TRANS)
736 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
737 if (fifo_isempty(txfifo))
740 UARTDescs[SER_UART0].sending = false;
743 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
747 #endif /* SER_UART0_BUS_TXOFF */
753 * Serial 1 TX interrupt handler
755 SIGNAL(SIG_UART1_DATA)
759 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
761 if (fifo_isempty(txfifo))
764 #ifndef SER_UART1_BUS_TXOFF
765 UARTDescs[SER_UART1].sending = false;
768 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
771 // Disable rx interrupt and tx, enable CTS interrupt
773 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
780 char c = fifo_pop(txfifo);
781 SER_UART1_BUS_TXCHAR(c);
787 #ifdef SER_UART1_BUS_TXOFF
789 * Serial port 1 TX complete interrupt handler.
791 * \sa port 0 TX complete handler.
793 SIGNAL(SIG_UART1_TRANS)
797 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
798 if (fifo_isempty(txfifo))
801 UARTDescs[SER_UART1].sending = false;
804 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
808 #endif /* SER_UART1_BUS_TXOFF */
810 #endif // AVR_HAS_UART1
814 * Serial 0 RX complete interrupt handler.
816 * This handler is interruptible.
817 * Interrupt are reenabled as soon as recv complete interrupt is
818 * disabled. Using INTERRUPT() is troublesome when the serial
819 * is heavily loaded, because an interrupt could be retriggered
820 * when executing the handler prologue before RXCIE is disabled.
822 * \note The code that re-enables interrupts is commented out
823 * because in some nasty cases the interrupt is retriggered.
824 * This is probably due to the RXC flag being set before
825 * RXCIE is cleared. Unfortunately the RXC flag is read-only
826 * and can't be cleared by code.
828 SIGNAL(SIG_UART0_RECV)
832 /* Disable Recv complete IRQ */
833 //UCSR0B &= ~BV(RXCIE);
836 /* Should be read before UDR */
837 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
839 /* To clear the RXC flag we must _always_ read the UDR even when we're
840 * not going to accept the incoming data, otherwise a new interrupt
841 * will occur once the handler terminates.
844 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
846 if (fifo_isfull(rxfifo))
847 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
850 fifo_push(rxfifo, c);
851 #if CONFIG_SER_HWHANDSHAKE
852 if (fifo_isfull(rxfifo))
857 /* Reenable receive complete int */
859 //UCSR0B |= BV(RXCIE);
868 * Serial 1 RX complete interrupt handler.
870 * This handler is interruptible.
871 * Interrupt are reenabled as soon as recv complete interrupt is
872 * disabled. Using INTERRUPT() is troublesome when the serial
873 * is heavily loaded, because an interrupt could be retriggered
874 * when executing the handler prologue before RXCIE is disabled.
876 * \see SIGNAL(SIG_UART0_RECV)
878 SIGNAL(SIG_UART1_RECV)
882 /* Disable Recv complete IRQ */
883 //UCSR1B &= ~BV(RXCIE);
886 /* Should be read before UDR */
887 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
889 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
890 * not going to accept the incoming data
893 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
894 //ASSERT_VALID_FIFO(rxfifo);
896 if (UNLIKELY(fifo_isfull(rxfifo)))
897 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
900 fifo_push(rxfifo, c);
901 #if CONFIG_SER_HWHANDSHAKE
902 if (fifo_isfull(rxfifo))
906 /* Re-enable receive complete int */
908 //UCSR1B |= BV(RXCIE);
913 #endif // AVR_HAS_UART1
917 * SPI interrupt handler
923 /* Read incoming byte. */
924 if (!fifo_isfull(&ser_spi->rxfifo))
925 fifo_push(&ser_spi->rxfifo, SPDR);
929 ser_spi->status |= SERRF_RXFIFOOVERRUN;
933 if (!fifo_isempty(&ser_spi->txfifo))
934 SPDR = fifo_pop(&ser_spi->txfifo);
936 UARTDescs[SER_SPI].sending = false;