4 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
5 * Copyright 2003,2004 Develer S.r.l. (http://www.develer.com/)
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 * Revision 1.9 2004/08/02 20:20:29 aleph
42 * Merge from project_ks
44 * Revision 1.8 2004/07/29 22:57:09 bernie
45 * Several tweaks to reduce code size on ATmega8.
47 * Revision 1.7 2004/07/18 21:54:23 bernie
48 * Add ATmega8 support.
50 * Revision 1.5 2004/06/27 15:25:40 aleph
51 * Add missing callbacks for SPI;
52 * Change UNUSED() macro to new version with two args;
53 * Use TX line filling only on the correct KBUS serial port;
54 * Fix nasty IRQ disabling bug in recv complete hander for port 1.
56 * Revision 1.4 2004/06/03 11:27:09 bernie
57 * Add dual-license information.
59 * Revision 1.3 2004/06/02 21:35:24 aleph
60 * Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
62 * Revision 1.2 2004/05/23 18:21:53 bernie
63 * Trim CVS logs and cleanup header info.
72 #include <mware/fifobuf.h>
74 #include <avr/signal.h>
77 /* Hardware handshake (RTS/CTS). */
79 #define RTS_ON do {} while (0)
82 #define RTS_OFF do {} while (0)
85 #define IS_CTS_ON true
88 /* External 485 transceiver on UART0 (to be overridden in "hw.h"). */
89 #if !defined(SER_UART0_485_INIT)
90 #if defined(SER_UART0_485_RX) || defined(SER_UART0_485_TX)
91 #error SER_UART0_485_INIT, SER_UART0_485_RX and SER_UART0_485_TX must be defined together
93 #define SER_UART0_485_INIT do {} while (0)
94 #define SER_UART0_485_TX do {} while (0)
95 /* SER_UART0_485_RX must not be defined! */
96 #elif !defined(SER_UART0_485_RX) || !defined(SER_UART0_485_TX)
97 #error SER_UART0_485_INIT, SER_UART0_485_RX and SER_UART0_485_TX must be defined together
100 /* External 485 transceiver on UART1 (to be overridden in "hw.h"). */
101 #ifndef SER_UART1_485_INIT
102 #if defined(SER_UART1_485_RX) || defined(SER_UART1_485_TX)
103 #error SER_UART1_485_INIT, SER_UART1_485_RX and SER_UART1_485_TX must be defined together
105 #define SER_UART1_485_INIT do {} while (0)
106 #define SER_UART1_485_TX do {} while (0)
107 /* SER_UART1_485_RX must not be defined! */
108 #elif !defined(SER_UART1_485_RX) || !defined(SER_UART1_485_TX)
109 #error SER_UART1_485_INIT, SER_UART1_485_RX and SER_UART1_485_TX must be defined together
113 /* SPI port and pin configuration */
114 #define SPI_PORT PORTB
116 #define SPI_SCK_BIT PORTB1
117 #define SPI_MOSI_BIT PORTB2
118 #define SPI_MISO_BIT PORTB3
121 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
122 #define AVR_HAS_UART1 1
123 #elif defined(__AVR_ATmega8__)
124 #define AVR_HAS_UART1 0
131 #define SIG_UART0_DATA SIG_UART_DATA
132 #define SIG_UART0_RECV SIG_UART_RECV
133 #elif defined(__AVR_ATmega103__)
134 #define AVR_HAS_UART1 0
139 #define SIG_UART0_DATA SIG_UART_DATA
140 #define SIG_UART0_RECV SIG_UART_RECV
142 #error Unknown architecture
146 /* Transmission fill byte */
147 #define SER_FILL_BYTE 0xAA
150 /* From the high-level serial driver */
151 extern struct Serial ser_handles[SER_CNT];
154 * These are to trick GCC into *not* using
155 * absolute addressing mode when accessing
156 * ser_handles, which is very expensive.
158 * Accessing through these pointers generates
159 * much shorter (and hopefully faster) code.
161 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
163 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
165 struct Serial *ser_spi = &ser_handles[SER_SPI];
168 static void uart0_enabletxirq(UNUSED(struct SerialHardware *, ctx))
170 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0)
171 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
172 #elif defined(SER_UART0_485_TX)
173 /* Disable receiver, enable transmitter, switch 485 transceiver. */
174 UCSR0B = BV(UDRIE) | BV(TXEN);
177 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
181 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
183 #if defined(ARCH_BOARD_KS) && (ARCH & ARCH_BOARD_KS)
184 /* Set TX port as input with pull-up enabled to avoid
185 noise on the remote RX when TX is disabled. */
187 DISABLE_IRQSAVE(flags);
190 ENABLE_IRQRESTORE(flags);
191 #endif /* ARCH_BOARD_KS */
193 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0)
195 * Set multiprocessor mode and 9 bit data frame.
196 * The receiver keep MPCM bit always on. When useful data
197 * is trasmitted the ninth bit is set and the receiver receive
199 * When useless fill bytes are sent the ninth bit is cleared
200 * and the receiver will ignore them.
203 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
205 UCSR0B = BV(RXCIE) | BV(RXEN);
212 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
217 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
219 /* Compute baud-rate period */
220 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
222 #ifndef __AVR_ATmega103__
223 UBRR0H = (period) >> 8;
227 DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
230 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
232 #ifndef __AVR_ATmega103__
233 UCSR0C |= (parity) << UPM0;
239 static void uart1_enabletxirq(UNUSED(struct SerialHardware *, _hw))
241 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1)
242 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
243 #elif defined(SER_UART1_485_TX)
244 /* Disable receiver, enable transmitter, switch 485 transceiver. */
245 UCSR1B = BV(UDRIE) | BV(TXEN);
248 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
252 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
254 /* Set TX port as input with pull-up enabled to avoid
255 * noise on the remote RX when TX is disabled */
257 DISABLE_IRQSAVE(flags);
260 ENABLE_IRQRESTORE(flags);
262 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1)
263 /*! See comment in uart0_init() */
265 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
267 UCSR1B = BV(RXCIE) | BV(RXEN);
273 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
278 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
280 /* Compute baud-rate period */
281 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
283 UBRR1H = (period) >> 8;
286 DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
289 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
291 UCSR1C |= (parity) << UPM0;
294 #endif // AVR_HAS_UART1
297 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
300 * Set MOSI and SCK ports out, MISO in.
302 * The ATmega64/128 datasheet explicitly states that the input/output
303 * state of the SPI pins is not significant, as when the SPI is
304 * active the I/O port are overrided.
305 * This is *blatantly FALSE*.
307 * Moreover, the MISO pin on the board_kc *must* be in high impedance
308 * state even when the SPI is off, because the line is wired together
309 * with the KBus serial RX, and the transmitter of the slave boards
310 * would be unable to drive the line.
312 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
313 SPI_DDR &= ~BV(SPI_MISO_BIT);
314 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
315 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
318 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
321 /* Set all pins as inputs */
322 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
325 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
330 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
336 #if CONFIG_SER_HWHANDSHAKE
338 //! This interrupt is triggered when the CTS line goes high
341 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
342 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
343 cbi(EIMSK, EIMSKB_CTS);
346 #endif // CONFIG_SER_HWHANDSHAKE
350 * Serial 0 TX interrupt handler
352 SIGNAL(SIG_UART0_DATA)
354 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
356 if (fifo_isempty(txfifo))
358 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0)
360 * To avoid audio interference: always transmit useless char.
361 * Send the byte with the ninth bit cleared, the receiver in MCPM mode
365 UDR0 = SER_FILL_BYTE;
366 #elif defined(SER_UART0_485_RX)
368 * - Disable UDR empty interrupt
369 * - Disable the transmitter (the in-progress transfer will complete)
370 * - Enable the transmit complete interrupt for the 485 tranceiver.
374 /* Disable UDR empty interrupt and transmitter */
375 UCSR0B = BV(RXCIE) | BV(RXEN);
378 #if CONFIG_SER_HWHANDSHAKE
381 // Disable rx interrupt and tx, enable CTS interrupt
382 UCSR0B = BV(RXCIE) | BV(RXEN);
383 sbi(EIFR, EIMSKB_CTS);
384 sbi(EIMSK, EIMSKB_CTS);
386 #endif // CONFIG_SER_HWHANDSHAKE
389 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 0)
390 /* Send with ninth bit set. Receiver in MCPM mode will receive it */
393 UDR0 = fifo_pop(txfifo);
397 #ifdef SER_UART0_485_RX
399 * Serial port 0 TX complete interrupt handler.
401 * This IRQ is usually disabled. The UDR-empty interrupt
402 * enables it when there's no more data to transmit.
403 * We need to wait until the last character has been
404 * transmitted before switching the 485 transceiver to
407 SIGNAL(SIG_UART0_TRANS)
409 /* Turn the 485 tranceiver into receive mode. */
412 /* Enable UART receiver and receive interrupt. */
413 UCSR0B = BV(RXCIE) | BV(RXEN);
415 #endif /* SER_UART0_485_RX */
421 * Serial 1 TX interrupt handler
423 SIGNAL(SIG_UART1_DATA)
425 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
427 if (fifo_isempty(txfifo))
429 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1)
431 * To avoid audio interference: always transmit useless char.
432 * Send the byte with the ninth bit cleared, the receiver in MCPM mode
436 UDR1 = SER_FILL_BYTE;
437 #elif defined(SER_UART1_485_RX)
439 * - Disable UDR empty interrupt
440 * - Disable the transmitter (the in-progress transfer will complete)
441 * - Enable the transmit complete interrupt for the 485 tranceiver.
445 /* Disable UDR empty interrupt and transmitter */
446 UCSR1B = BV(RXCIE) | BV(RXEN);
449 #if CONFIG_SER_HWHANDSHAKE
452 // Disable rx interrupt and tx, enable CTS interrupt
453 UCSR1B = BV(RXCIE) | BV(RXEN);
454 sbi(EIFR, EIMSKB_CTS);
455 sbi(EIMSK, EIMSKB_CTS);
457 #endif // CONFIG_SER_HWHANDSHAKE
460 #if CONFIG_SER_TXFILL && (CONFIG_KBUS_PORT == 1)
461 /* Send with ninth bit set. Receiver in MCPM mode will receive it */
464 UDR1 = fifo_pop(txfifo);
468 #ifdef SER_UART1_485_RX
470 * Serial port 1 TX complete interrupt handler.
472 * \sa port 0 TX complete handler.
474 SIGNAL(SIG_UART1_TRANS)
476 /* Turn the 485 tranceiver into receive mode. */
479 /* Enable UART receiver and receive interrupt. */
480 UCSR1B = BV(RXCIE) | BV(RXEN);
482 #endif /* SER_UART1_485_RX */
484 #endif // AVR_HAS_UART1
488 * Serial 0 RX complete interrupt handler.
490 * This handler is interruptible.
491 * Interrupt are reenabled as soon as recv complete interrupt is
492 * disabled. Using INTERRUPT() is troublesome when the serial
493 * is heavily loaded, because an interrupt could be retriggered
494 * when executing the handler prologue before RXCIE is disabled.
496 SIGNAL(SIG_UART0_RECV)
498 /* Disable Recv complete IRQ */
499 UCSR0B &= ~BV(RXCIE);
502 /* Should be read before UDR */
503 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
505 /* To clear the RXC flag we must _always_ read the UDR even when we're
506 * not going to accept the incoming data, otherwise a new interrupt
507 * will occur once the handler terminates.
510 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
512 if (fifo_isfull(rxfifo))
513 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
516 fifo_push(rxfifo, c);
517 #if CONFIG_SER_HWHANDSHAKE
518 if (fifo_isfull(rxfifo))
523 /* Reenable receive complete int */
531 * Serial 1 RX complete interrupt handler.
533 * This handler is interruptible.
534 * Interrupt are reenabled as soon as recv complete interrupt is
535 * disabled. Using INTERRUPT() is troublesome when the serial
536 * is heavily loaded, because an interrupt could be retriggered
537 * when executing the handler prologue before RXCIE is disabled.
539 SIGNAL(SIG_UART1_RECV)
541 /* Disable Recv complete IRQ */
542 UCSR1B &= ~BV(RXCIE);
545 /* Should be read before UDR */
546 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
548 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
549 * not going to accept the incoming data
552 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
554 if (fifo_isfull(rxfifo))
555 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
558 fifo_push(rxfifo, c);
559 #if CONFIG_SER_HWHANDSHAKE
560 if (fifo_isfull(rxfifo))
564 /* Reenable receive complete int */
568 #endif // AVR_HAS_UART1
572 * SPI Flag: true if we are transmitting/receiving with the SPI.
574 * This kludge is necessary because the SPI sends and receives bytes
575 * at the same time and the SPI IRQ is unique for send/receive.
576 * The only way to start transmission is to write data in SPDR (this
577 * is done by spi_starttx()). We do this *only* if a transfer is
578 * not already started.
580 static volatile bool spi_sending = false;
582 static void spi_starttx(UNUSED(struct SerialHardware *, ctx))
586 DISABLE_IRQSAVE(flags);
588 /* Send data only if the SPI is not already transmitting */
589 if (!spi_sending && !fifo_isempty(&ser_spi->txfifo))
591 SPDR = fifo_pop(&ser_spi->txfifo);
595 ENABLE_IRQRESTORE(flags);
599 * SPI interrupt handler
603 /* Read incoming byte. */
604 if (!fifo_isfull(&ser_spi->rxfifo))
605 fifo_push(&ser_spi->rxfifo, SPDR);
609 ser_spi->status |= SERRF_RXFIFOOVERRUN;
613 if (!fifo_isempty(&ser_spi->txfifo))
614 SPDR = fifo_pop(&ser_spi->txfifo);
620 static const struct SerialHardwareVT UART0_VT =
623 .cleanup = uart0_cleanup,
624 .setbaudrate = uart0_setbaudrate,
625 .setparity = uart0_setparity,
626 .enabletxirq = uart0_enabletxirq,
630 static const struct SerialHardwareVT UART1_VT =
633 .cleanup = uart1_cleanup,
634 .setbaudrate = uart1_setbaudrate,
635 .setparity = uart1_setparity,
636 .enabletxirq = uart1_enabletxirq,
638 #endif // AVR_HAS_UART1
640 static const struct SerialHardwareVT SPI_VT =
643 .cleanup = spi_cleanup,
644 .setbaudrate = spi_setbaudrate,
645 .setparity = spi_setparity,
646 .enabletxirq = spi_starttx,
649 static struct SerialHardware UARTDescs[SER_CNT] =
651 { .table = &UART0_VT },
653 { .table = &UART1_VT },
655 { .table = &SPI_VT },
658 struct SerialHardware* ser_hw_getdesc(int unit)
660 ASSERT(unit < SER_CNT);
661 return &UARTDescs[unit];