4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See README.devlib for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.28 2005/11/04 16:20:02 bernie
42 *#* Fix reference to README.devlib in header.
44 *#* Revision 1.27 2005/07/03 15:19:31 bernie
47 *#* Revision 1.26 2005/04/11 19:10:27 bernie
48 *#* Include top-level headers from cfg/ subdir.
50 *#* Revision 1.25 2005/01/25 08:37:26 bernie
51 *#* CONFIG_SER_HWHANDSHAKE fixes.
53 *#* Revision 1.24 2005/01/14 00:49:16 aleph
54 *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
56 *#* Revision 1.23 2005/01/11 18:09:07 aleph
57 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
59 *#* Revision 1.22 2004/12/31 17:47:45 bernie
60 *#* Rename UNUSED() to UNUSED_ARG().
62 *#* Revision 1.21 2004/12/13 12:07:06 bernie
63 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
65 *#* Revision 1.20 2004/12/13 11:51:43 bernie
66 *#* Fix a latent bug with reentrant serial IRQs.
68 *#* Revision 1.19 2004/12/13 11:51:08 bernie
69 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
71 *#* Revision 1.18 2004/12/08 08:03:48 bernie
74 *#* Revision 1.17 2004/10/19 07:52:35 bernie
75 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
77 *#* Revision 1.16 2004/10/03 18:45:48 bernie
78 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
80 *#* Revision 1.15 2004/09/14 21:05:36 bernie
81 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
83 *#* Revision 1.14 2004/09/06 21:50:00 bernie
86 *#* Revision 1.13 2004/09/06 21:40:50 bernie
87 *#* Move buffer handling in chip-specific driver.
89 *#* Revision 1.12 2004/08/29 22:06:10 bernie
90 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
92 *#* Revision 1.10 2004/08/10 06:30:41 bernie
93 *#* Major redesign of serial bus policy handling.
95 *#* Revision 1.9 2004/08/02 20:20:29 aleph
96 *#* Merge from project_ks
98 *#* Revision 1.8 2004/07/29 22:57:09 bernie
99 *#* Several tweaks to reduce code size on ATmega8.
101 *#* Revision 1.7 2004/07/18 21:54:23 bernie
102 *#* Add ATmega8 support.
104 *#* Revision 1.5 2004/06/27 15:25:40 aleph
105 *#* Add missing callbacks for SPI;
106 *#* Change UNUSED() macro to new version with two args;
107 *#* Use TX line filling only on the correct KBUS serial port;
108 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
110 *#* Revision 1.4 2004/06/03 11:27:09 bernie
111 *#* Add dual-license information.
113 *#* Revision 1.3 2004/06/02 21:35:24 aleph
114 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
116 *#* Revision 1.2 2004/05/23 18:21:53 bernie
117 *#* Trim CVS logs and cleanup header info.
123 #include <cfg/config.h>
124 #include "hw.h" /* Required for bus macros overrides */
126 #include <cfg/debug.h>
127 #include <drv/timer.h>
128 #include <mware/fifobuf.h>
130 #include <avr/signal.h>
134 #if !CONFIG_SER_HWHANDSHAKE
136 * \name Hardware handshake (RTS/CTS).
139 #define RTS_ON do {} while (0)
140 #define RTS_OFF do {} while (0)
141 #define IS_CTS_ON true
142 #define EIMSKF_CTS 0 /*!< Dummy value, must be overridden */
148 * \name Overridable serial bus hooks
150 * These can be redefined in hw.h to implement
151 * special bus policies such as half-duplex, 485, etc.
155 * TXBEGIN TXCHAR TXEND TXOFF
156 * | __________|__________ | |
159 * ______ __ __ __ __ __ __ ________________
160 * \/ \/ \/ \/ \/ \/ \/
161 * ______/\__/\__/\__/\__/\__/\__/
167 #ifndef SER_UART0_BUS_TXINIT
169 * Default TXINIT macro - invoked in uart0_init()
171 * - Enable both the receiver and the transmitter
172 * - Enable only the RX complete interrupt
174 #define SER_UART0_BUS_TXINIT do { \
175 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
179 #ifndef SER_UART0_BUS_TXBEGIN
181 * Invoked before starting a transmission
183 * - Enable both the receiver and the transmitter
184 * - Enable both the RX complete and UDR empty interrupts
186 #define SER_UART0_BUS_TXBEGIN do { \
187 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
191 #ifndef SER_UART0_BUS_TXCHAR
193 * Invoked to send one character.
195 #define SER_UART0_BUS_TXCHAR(c) do { \
200 #ifndef SER_UART0_BUS_TXEND
202 * Invoked as soon as the txfifo becomes empty
204 * - Keep both the receiver and the transmitter enabled
205 * - Keep the RX complete interrupt enabled
206 * - Disable the UDR empty interrupt
208 #define SER_UART0_BUS_TXEND do { \
209 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
213 #ifndef SER_UART0_BUS_TXOFF
215 * \def SER_UART0_BUS_TXOFF
217 * Invoked after the last character has been transmitted
219 * The default is no action.
222 #define SER_UART0_BUS_TXOFF
226 #ifndef SER_UART1_BUS_TXINIT
227 /*! \sa SER_UART0_BUS_TXINIT */
228 #define SER_UART1_BUS_TXINIT do { \
229 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
232 #ifndef SER_UART1_BUS_TXBEGIN
233 /*! \sa SER_UART0_BUS_TXBEGIN */
234 #define SER_UART1_BUS_TXBEGIN do { \
235 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
238 #ifndef SER_UART1_BUS_TXCHAR
239 /*! \sa SER_UART0_BUS_TXCHAR */
240 #define SER_UART1_BUS_TXCHAR(c) do { \
244 #ifndef SER_UART1_BUS_TXEND
245 /*! \sa SER_UART0_BUS_TXEND */
246 #define SER_UART1_BUS_TXEND do { \
247 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
250 #ifndef SER_UART1_BUS_TXOFF
252 * \def SER_UART1_BUS_TXOFF
254 * \see SER_UART0_BUS_TXOFF
257 #define SER_UART1_BUS_TXOFF
264 * \name Overridable SPI hooks
266 * These can be redefined in hw.h to implement
267 * special bus policies such as slave select pin handling, etc.
271 #ifndef SER_SPI_BUS_TXINIT
273 * Default TXINIT macro - invoked in spi_init()
274 * The default is no action.
276 #define SER_SPI_BUS_TXINIT
279 #ifndef SER_SPI_BUS_TXCLOSE
281 * Invoked after the last character has been transmitted.
282 * The default is no action.
284 #define SER_SPI_BUS_TXCLOSE
289 /* SPI port and pin configuration */
290 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
291 #define SPI_PORT PORTB
293 #define SPI_SCK_BIT PB1
294 #define SPI_MOSI_BIT PB2
295 #define SPI_MISO_BIT PB3
296 #elif CPU_AVR_ATMEGA8
297 #define SPI_PORT PORTB
299 #define SPI_SCK_BIT PB5
300 #define SPI_MOSI_BIT PB3
301 #define SPI_MISO_BIT PB4
303 #error Unknown architecture
306 /* USART register definitions */
307 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
308 #define AVR_HAS_UART1 1
309 #elif CPU_AVR_ATMEGA8
310 #define AVR_HAS_UART1 0
317 #define SIG_UART0_DATA SIG_UART_DATA
318 #define SIG_UART0_RECV SIG_UART_RECV
319 #define SIG_UART0_TRANS SIG_UART_TRANS
320 #elif CPU_AVR_ATMEGA103
321 #define AVR_HAS_UART1 0
326 #define SIG_UART0_DATA SIG_UART_DATA
327 #define SIG_UART0_RECV SIG_UART_RECV
328 #define SIG_UART0_TRANS SIG_UART_TRANS
330 #error Unknown architecture
335 * \def CONFIG_SER_STROBE
337 * This is a debug facility that can be used to
338 * monitor SER interrupt activity on an external pin.
340 * To use strobes, redefine the macros SER_STROBE_ON,
341 * SER_STROBE_OFF and SER_STROBE_INIT and set
342 * CONFIG_SER_STROBE to 1.
344 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
345 #define SER_STROBE_ON do {/*nop*/} while(0)
346 #define SER_STROBE_OFF do {/*nop*/} while(0)
347 #define SER_STROBE_INIT do {/*nop*/} while(0)
351 /* From the high-level serial driver */
352 extern struct Serial ser_handles[SER_CNT];
354 /* TX and RX buffers */
355 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
356 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
358 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
359 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
361 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
362 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
366 * Internal hardware state structure
368 * The \a sending variable is true while the transmission
369 * interrupt is retriggering itself.
371 * For the USARTs the \a sending flag is useful for taking specific
372 * actions before sending a burst of data, at the start of a trasmission
373 * but not before every char sent.
375 * For the SPI, this flag is necessary because the SPI sends and receives
376 * bytes at the same time and the SPI IRQ is unique for send/receive.
377 * The only way to start transmission is to write data in SPDR (this
378 * is done by spi_starttx()). We do this *only* if a transfer is
379 * not already started.
383 struct SerialHardware hw;
384 volatile bool sending;
389 * These are to trick GCC into *not* using absolute addressing mode
390 * when accessing ser_handles, which is very expensive.
392 * Accessing through these pointers generates much shorter
393 * (and hopefully faster) code.
395 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
397 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
399 struct Serial *ser_spi = &ser_handles[SER_SPI];
406 static void uart0_init(
407 UNUSED_ARG(struct SerialHardware *, _hw),
408 UNUSED_ARG(struct Serial *, ser))
410 SER_UART0_BUS_TXINIT;
415 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
420 static void uart0_enabletxirq(struct SerialHardware *_hw)
422 struct AvrSerial *hw = (struct AvrSerial *)_hw;
425 * WARNING: racy code here! The tx interrupt sets hw->sending to false
426 * when it runs with an empty fifo. The order of statements in the
432 SER_UART0_BUS_TXBEGIN;
436 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
438 /* Compute baud-rate period */
439 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
441 #if !CPU_AVR_ATMEGA103
442 UBRR0H = (period) >> 8;
446 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
449 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
451 #if !CPU_AVR_ATMEGA103
452 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
458 static void uart1_init(
459 UNUSED_ARG(struct SerialHardware *, _hw),
460 UNUSED_ARG(struct Serial *, ser))
462 SER_UART1_BUS_TXINIT;
467 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
472 static void uart1_enabletxirq(struct SerialHardware *_hw)
474 struct AvrSerial *hw = (struct AvrSerial *)_hw;
477 * WARNING: racy code here! The tx interrupt
478 * sets hw->sending to false when it runs with
479 * an empty fifo. The order of the statements
480 * in the if-block matters.
485 SER_UART1_BUS_TXBEGIN;
489 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
491 /* Compute baud-rate period */
492 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
494 UBRR1H = (period) >> 8;
497 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
500 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
502 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
505 #endif // AVR_HAS_UART1
507 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
510 * Set MOSI and SCK ports out, MISO in.
512 * The ATmega64/128 datasheet explicitly states that the input/output
513 * state of the SPI pins is not significant, as when the SPI is
514 * active the I/O port are overrided.
515 * This is *blatantly FALSE*.
517 * Moreover, the MISO pin on the board_kc *must* be in high impedance
518 * state even when the SPI is off, because the line is wired together
519 * with the KBus serial RX, and the transmitter of the slave boards
520 * would be unable to drive the line.
522 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
523 SPI_DDR &= ~BV(SPI_MISO_BIT);
524 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
525 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
532 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
538 /* Set all pins as inputs */
539 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
542 static void spi_starttx(struct SerialHardware *_hw)
544 struct AvrSerial *hw = (struct AvrSerial *)_hw;
547 IRQ_SAVE_DISABLE(flags);
549 /* Send data only if the SPI is not already transmitting */
550 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
553 SPDR = fifo_pop(&ser_spi->txfifo);
559 static void spi_setbaudrate(
560 UNUSED_ARG(struct SerialHardware *, _hw),
561 UNUSED_ARG(unsigned long, rate))
566 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
571 static bool tx_sending(struct SerialHardware* _hw)
573 struct AvrSerial *hw = (struct AvrSerial *)_hw;
579 // FIXME: move into compiler.h? Ditch?
581 #define C99INIT(name,val) .name = val
582 #elif defined(__GNUC__)
583 #define C99INIT(name,val) name: val
585 #warning No designated initializers, double check your code
586 #define C99INIT(name,val) (val)
590 * High-level interface data structures
592 static const struct SerialHardwareVT UART0_VT =
594 C99INIT(init, uart0_init),
595 C99INIT(cleanup, uart0_cleanup),
596 C99INIT(setBaudrate, uart0_setbaudrate),
597 C99INIT(setParity, uart0_setparity),
598 C99INIT(txStart, uart0_enabletxirq),
599 C99INIT(txSending, tx_sending),
603 static const struct SerialHardwareVT UART1_VT =
605 C99INIT(init, uart1_init),
606 C99INIT(cleanup, uart1_cleanup),
607 C99INIT(setBaudrate, uart1_setbaudrate),
608 C99INIT(setParity, uart1_setparity),
609 C99INIT(txStart, uart1_enabletxirq),
610 C99INIT(txSending, tx_sending),
612 #endif // AVR_HAS_UART1
614 static const struct SerialHardwareVT SPI_VT =
616 C99INIT(init, spi_init),
617 C99INIT(cleanup, spi_cleanup),
618 C99INIT(setBaudrate, spi_setbaudrate),
619 C99INIT(setParity, spi_setparity),
620 C99INIT(txStart, spi_starttx),
621 C99INIT(txSending, tx_sending),
624 static struct AvrSerial UARTDescs[SER_CNT] =
628 C99INIT(table, &UART0_VT),
629 C99INIT(txbuffer, uart0_txbuffer),
630 C99INIT(rxbuffer, uart0_rxbuffer),
631 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
632 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
634 C99INIT(sending, false),
639 C99INIT(table, &UART1_VT),
640 C99INIT(txbuffer, uart1_txbuffer),
641 C99INIT(rxbuffer, uart1_rxbuffer),
642 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
643 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
645 C99INIT(sending, false),
650 C99INIT(table, &SPI_VT),
651 C99INIT(txbuffer, spi_txbuffer),
652 C99INIT(rxbuffer, spi_rxbuffer),
653 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
654 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
656 C99INIT(sending, false),
660 struct SerialHardware* ser_hw_getdesc(int unit)
662 ASSERT(unit < SER_CNT);
663 return &UARTDescs[unit].hw;
671 #if CONFIG_SER_HWHANDSHAKE
673 //! This interrupt is triggered when the CTS line goes high
676 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
677 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
678 EIMSK &= ~EIMSKF_CTS;
681 #endif // CONFIG_SER_HWHANDSHAKE
685 * Serial 0 TX interrupt handler
687 SIGNAL(SIG_UART0_DATA)
691 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
693 if (fifo_isempty(txfifo))
696 #ifndef SER_UART0_BUS_TXOFF
697 UARTDescs[SER_UART0].sending = false;
700 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
703 // Disable rx interrupt and tx, enable CTS interrupt
705 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
712 char c = fifo_pop(txfifo);
713 SER_UART0_BUS_TXCHAR(c);
719 #ifdef SER_UART0_BUS_TXOFF
721 * Serial port 0 TX complete interrupt handler.
723 * This IRQ is usually disabled. The UDR-empty interrupt
724 * enables it when there's no more data to transmit.
725 * We need to wait until the last character has been
726 * transmitted before switching the 485 transceiver to
729 * The txfifo might have been refilled by putchar() while
730 * we were waiting for the transmission complete interrupt.
731 * In this case, we must restart the UDR empty interrupt,
732 * otherwise we'd stop the serial port with some data
733 * still pending in the buffer.
735 SIGNAL(SIG_UART0_TRANS)
739 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
740 if (fifo_isempty(txfifo))
743 UARTDescs[SER_UART0].sending = false;
746 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
750 #endif /* SER_UART0_BUS_TXOFF */
756 * Serial 1 TX interrupt handler
758 SIGNAL(SIG_UART1_DATA)
762 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
764 if (fifo_isempty(txfifo))
767 #ifndef SER_UART1_BUS_TXOFF
768 UARTDescs[SER_UART1].sending = false;
771 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
774 // Disable rx interrupt and tx, enable CTS interrupt
776 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
783 char c = fifo_pop(txfifo);
784 SER_UART1_BUS_TXCHAR(c);
790 #ifdef SER_UART1_BUS_TXOFF
792 * Serial port 1 TX complete interrupt handler.
794 * \sa port 0 TX complete handler.
796 SIGNAL(SIG_UART1_TRANS)
800 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
801 if (fifo_isempty(txfifo))
804 UARTDescs[SER_UART1].sending = false;
807 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
811 #endif /* SER_UART1_BUS_TXOFF */
813 #endif // AVR_HAS_UART1
817 * Serial 0 RX complete interrupt handler.
819 * This handler is interruptible.
820 * Interrupt are reenabled as soon as recv complete interrupt is
821 * disabled. Using INTERRUPT() is troublesome when the serial
822 * is heavily loaded, because an interrupt could be retriggered
823 * when executing the handler prologue before RXCIE is disabled.
825 * \note The code that re-enables interrupts is commented out
826 * because in some nasty cases the interrupt is retriggered.
827 * This is probably due to the RXC flag being set before
828 * RXCIE is cleared. Unfortunately the RXC flag is read-only
829 * and can't be cleared by code.
831 SIGNAL(SIG_UART0_RECV)
835 /* Disable Recv complete IRQ */
836 //UCSR0B &= ~BV(RXCIE);
839 /* Should be read before UDR */
840 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
842 /* To clear the RXC flag we must _always_ read the UDR even when we're
843 * not going to accept the incoming data, otherwise a new interrupt
844 * will occur once the handler terminates.
847 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
849 if (fifo_isfull(rxfifo))
850 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
853 fifo_push(rxfifo, c);
854 #if CONFIG_SER_HWHANDSHAKE
855 if (fifo_isfull(rxfifo))
860 /* Reenable receive complete int */
862 //UCSR0B |= BV(RXCIE);
871 * Serial 1 RX complete interrupt handler.
873 * This handler is interruptible.
874 * Interrupt are reenabled as soon as recv complete interrupt is
875 * disabled. Using INTERRUPT() is troublesome when the serial
876 * is heavily loaded, because an interrupt could be retriggered
877 * when executing the handler prologue before RXCIE is disabled.
879 * \see SIGNAL(SIG_UART0_RECV)
881 SIGNAL(SIG_UART1_RECV)
885 /* Disable Recv complete IRQ */
886 //UCSR1B &= ~BV(RXCIE);
889 /* Should be read before UDR */
890 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
892 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
893 * not going to accept the incoming data
896 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
897 //ASSERT_VALID_FIFO(rxfifo);
899 if (UNLIKELY(fifo_isfull(rxfifo)))
900 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
903 fifo_push(rxfifo, c);
904 #if CONFIG_SER_HWHANDSHAKE
905 if (fifo_isfull(rxfifo))
909 /* Re-enable receive complete int */
911 //UCSR1B |= BV(RXCIE);
916 #endif // AVR_HAS_UART1
920 * SPI interrupt handler
926 /* Read incoming byte. */
927 if (!fifo_isfull(&ser_spi->rxfifo))
928 fifo_push(&ser_spi->rxfifo, SPDR);
932 ser_spi->status |= SERRF_RXFIFOOVERRUN;
936 if (!fifo_isempty(&ser_spi->txfifo))
937 SPDR = fifo_pop(&ser_spi->txfifo);
939 UARTDescs[SER_SPI].sending = false;