4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.14 2004/09/06 21:50:00 bernie
44 *#* Revision 1.13 2004/09/06 21:40:50 bernie
45 *#* Move buffer handling in chip-specific driver.
47 *#* Revision 1.12 2004/08/29 22:06:10 bernie
48 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
50 *#* Revision 1.10 2004/08/10 06:30:41 bernie
51 *#* Major redesign of serial bus policy handling.
53 *#* Revision 1.9 2004/08/02 20:20:29 aleph
54 *#* Merge from project_ks
56 *#* Revision 1.8 2004/07/29 22:57:09 bernie
57 *#* Several tweaks to reduce code size on ATmega8.
59 *#* Revision 1.7 2004/07/18 21:54:23 bernie
60 *#* Add ATmega8 support.
62 *#* Revision 1.5 2004/06/27 15:25:40 aleph
63 *#* Add missing callbacks for SPI;
64 *#* Change UNUSED() macro to new version with two args;
65 *#* Use TX line filling only on the correct KBUS serial port;
66 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
68 *#* Revision 1.4 2004/06/03 11:27:09 bernie
69 *#* Add dual-license information.
71 *#* Revision 1.3 2004/06/02 21:35:24 aleph
72 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
74 *#* Revision 1.2 2004/05/23 18:21:53 bernie
75 *#* Trim CVS logs and cleanup header info.
82 #include "hw.h" /* Required for bus macros overrides */
84 #include <drv/kdebug.h>
85 #include <drv/timer.h>
86 #include <mware/fifobuf.h>
88 #include <avr/signal.h>
92 * \name Hardware handshake (RTS/CTS).
96 #define RTS_ON do {} while (0)
99 #define RTS_OFF do {} while (0)
102 #define IS_CTS_ON true
105 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
111 * \name Overridable serial bus hooks
113 * These can be redefined in hw.h to implement
114 * special bus policies such as half-duplex, 485, etc.
118 * TXBEGIN TXCHAR TXEND TXOFF
119 * | __________|__________ | |
122 * ______ __ __ __ __ __ __ ________________
123 * \/ \/ \/ \/ \/ \/ \/
124 * ______/\__/\__/\__/\__/\__/\__/
130 #ifndef SER_UART0_BUS_TXINIT
132 * Default TXINIT macro - invoked in uart0_init()
134 * - Enable both the receiver and the transmitter
135 * - Enable only the RX complete interrupt
137 #define SER_UART0_BUS_TXINIT do { \
138 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
142 #ifndef SER_UART0_BUS_TXBEGIN
144 * Invoked before starting a transmission
146 * - Enable both the receiver and the transmitter
147 * - Enable both the RX complete and UDR empty interrupts
149 #define SER_UART0_BUS_TXBEGIN do { \
150 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
154 #ifndef SER_UART0_BUS_TXCHAR
156 * Invoked to send one character.
158 #define SER_UART0_BUS_TXCHAR(c) do { \
163 #ifndef SER_UART0_BUS_TXEND
165 * Invoked as soon as the txfifo becomes empty
167 * - Keep both the receiver and the transmitter enabled
168 * - Keep the RX complete interrupt enabled
169 * - Disable the UDR empty interrupt
171 #define SER_UART0_BUS_TXEND do { \
172 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
176 #ifndef SER_UART0_BUS_TXOFF
178 * \def SER_UART0_BUS_TXOFF
180 * Invoked after the last character has been transmitted
182 * The default is no action.
186 #ifndef SER_UART1_BUS_TXINIT
187 /*! \sa SER_UART0_BUS_TXINIT */
188 #define SER_UART1_BUS_TXINIT do { \
189 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
192 #ifndef SER_UART1_BUS_TXBEGIN
193 /*! \sa SER_UART0_BUS_TXBEGIN */
194 #define SER_UART1_BUS_TXBEGIN do { \
195 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
198 #ifndef SER_UART1_BUS_TXCHAR
199 /*! \sa SER_UART0_BUS_TXCHAR */
200 #define SER_UART1_BUS_TXCHAR(c) do { \
204 #ifndef SER_UART1_BUS_TXEND
205 /*! \sa SER_UART0_BUS_TXEND */
206 #define SER_UART1_BUS_TXEND do { \
207 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
210 #ifndef SER_UART1_BUS_TXOFF
212 * \def SER_UART1_BUS_TXOFF
214 * \see SER_UART0_BUS_TXOFF
220 /* SPI port and pin configuration */
221 #define SPI_PORT PORTB
223 #define SPI_SCK_BIT PORTB1
224 #define SPI_MOSI_BIT PORTB2
225 #define SPI_MISO_BIT PORTB3
227 /* USART registers definitions */
228 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
229 #define AVR_HAS_UART1 1
230 #elif defined(__AVR_ATmega8__)
231 #define AVR_HAS_UART1 0
238 #define SIG_UART0_DATA SIG_UART_DATA
239 #define SIG_UART0_RECV SIG_UART_RECV
240 #elif defined(__AVR_ATmega103__)
241 #define AVR_HAS_UART1 0
246 #define SIG_UART0_DATA SIG_UART_DATA
247 #define SIG_UART0_RECV SIG_UART_RECV
249 #error Unknown architecture
254 * \def CONFIG_SER_STROBE
256 * This is a debug facility that can be used to
257 * monitor SER interrupt activity on an external pin.
259 * To use strobes, redefine the macros SER_STROBE_ON,
260 * SER_STROBE_OFF and SER_STROBE_INIT and set
261 * CONFIG_SER_STROBE to 1.
263 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
264 #define SER_STROBE_ON do {/*nop*/} while(0)
265 #define SER_STROBE_OFF do {/*nop*/} while(0)
266 #define SER_STROBE_INIT do {/*nop*/} while(0)
270 /* From the high-level serial driver */
271 extern struct Serial ser_handles[SER_CNT];
273 /* TX and RX buffers */
274 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
275 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
277 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
278 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
280 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
281 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
285 * Internal hardware state structure
287 * The \a sending variable is true while the transmission
288 * interrupt is retriggering itself.
290 * For the USARTs the \a sending flag is useful for taking specific
291 * actions before sending a burst of data, at the start of a trasmission
292 * but not before every char sent.
294 * For the SPI, this flag is necessary because the SPI sends and receives
295 * bytes at the same time and the SPI IRQ is unique for send/receive.
296 * The only way to start transmission is to write data in SPDR (this
297 * is done by spi_starttx()). We do this *only* if a transfer is
298 * not already started.
302 struct SerialHardware hw;
303 volatile bool sending;
308 * These are to trick GCC into *not* using
309 * absolute addressing mode when accessing
310 * ser_handles, which is very expensive.
312 * Accessing through these pointers generates
313 * much shorter (and hopefully faster) code.
315 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
317 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
319 struct Serial *ser_spi = &ser_handles[SER_SPI];
326 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
328 SER_UART0_BUS_TXINIT;
332 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
337 static void uart0_enabletxirq(struct SerialHardware *_hw)
339 struct AvrSerial *hw = (struct AvrSerial *)_hw;
342 * WARNING: racy code here! The tx interrupt
343 * sets hw->sending to false when it runs with
344 * an empty fifo. The order of the statements
345 * in the if-block matters.
350 SER_UART0_BUS_TXBEGIN;
354 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
356 /* Compute baud-rate period */
357 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
359 #ifndef __AVR_ATmega103__
360 UBRR0H = (period) >> 8;
364 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
367 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
369 #ifndef __AVR_ATmega103__
370 UCSR0C |= (parity) << UPM0;
376 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
378 SER_UART1_BUS_TXINIT;
383 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
388 static void uart1_enabletxirq(struct SerialHardware *_hw)
390 struct AvrSerial *hw = (struct AvrSerial *)_hw;
393 * WARNING: racy code here! The tx interrupt
394 * sets hw->sending to false when it runs with
395 * an empty fifo. The order of the statements
396 * in the if-block matters.
401 SER_UART1_BUS_TXBEGIN;
405 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
407 /* Compute baud-rate period */
408 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
410 UBRR1H = (period) >> 8;
413 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
416 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
418 UCSR1C |= (parity) << UPM0;
421 #endif // AVR_HAS_UART1
423 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
426 * Set MOSI and SCK ports out, MISO in.
428 * The ATmega64/128 datasheet explicitly states that the input/output
429 * state of the SPI pins is not significant, as when the SPI is
430 * active the I/O port are overrided.
431 * This is *blatantly FALSE*.
433 * Moreover, the MISO pin on the board_kc *must* be in high impedance
434 * state even when the SPI is off, because the line is wired together
435 * with the KBus serial RX, and the transmitter of the slave boards
436 * would be unable to drive the line.
438 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
439 SPI_DDR &= ~BV(SPI_MISO_BIT);
440 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
441 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
444 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
447 /* Set all pins as inputs */
448 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
451 static void spi_starttx(struct SerialHardware *_hw)
453 struct AvrSerial *hw = (struct AvrSerial *)_hw;
456 DISABLE_IRQSAVE(flags);
458 /* Send data only if the SPI is not already transmitting */
459 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
462 SPDR = fifo_pop(&ser_spi->txfifo);
465 ENABLE_IRQRESTORE(flags);
468 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
473 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
481 * High-level interface data structures
483 static const struct SerialHardwareVT UART0_VT =
486 .cleanup = uart0_cleanup,
487 .setbaudrate = uart0_setbaudrate,
488 .setparity = uart0_setparity,
489 .enabletxirq = uart0_enabletxirq,
493 static const struct SerialHardwareVT UART1_VT =
496 .cleanup = uart1_cleanup,
497 .setbaudrate = uart1_setbaudrate,
498 .setparity = uart1_setparity,
499 .enabletxirq = uart1_enabletxirq,
501 #endif // AVR_HAS_UART1
503 static const struct SerialHardwareVT SPI_VT =
506 .cleanup = spi_cleanup,
507 .setbaudrate = spi_setbaudrate,
508 .setparity = spi_setparity,
509 .enabletxirq = spi_starttx,
512 static struct AvrSerial UARTDescs[SER_CNT] =
517 .txbuffer = uart0_txbuffer,
518 .rxbuffer = uart0_rxbuffer,
519 .txbuffer_size = CONFIG_UART0_TXBUFSIZE,
520 .rxbuffer_size = CONFIG_UART0_RXBUFSIZE,
528 .txbuffer = uart1_txbuffer,
529 .rxbuffer = uart1_rxbuffer,
530 .txbuffer_size = CONFIG_UART1_TXBUFSIZE,
531 .rxbuffer_size = CONFIG_UART1_RXBUFSIZE,
539 .txbuffer = spi_txbuffer,
540 .rxbuffer = spi_rxbuffer,
541 .txbuffer_size = CONFIG_SPI_TXBUFSIZE,
542 .rxbuffer_size = CONFIG_SPI_RXBUFSIZE,
548 struct SerialHardware* ser_hw_getdesc(int unit)
550 ASSERT(unit < SER_CNT);
551 return &UARTDescs[unit].hw;
560 #if CONFIG_SER_HWHANDSHAKE
562 //! This interrupt is triggered when the CTS line goes high
565 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
566 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
567 cbi(EIMSK, EIMSKB_CTS);
570 #endif // CONFIG_SER_HWHANDSHAKE
574 * Serial 0 TX interrupt handler
576 SIGNAL(SIG_UART0_DATA)
580 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
582 if (fifo_isempty(txfifo))
585 #ifndef SER_UART0_BUS_TXOFF
586 UARTDescs[SER_UART0].sending = false;
589 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
592 // Disable rx interrupt and tx, enable CTS interrupt
594 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
595 sbi(EIFR, EIMSKB_CTS);
596 sbi(EIMSK, EIMSKB_CTS);
601 char c = fifo_pop(txfifo);
602 SER_UART0_BUS_TXCHAR(c);
608 #ifdef SER_UART0_BUS_TXOFF
610 * Serial port 0 TX complete interrupt handler.
612 * This IRQ is usually disabled. The UDR-empty interrupt
613 * enables it when there's no more data to transmit.
614 * We need to wait until the last character has been
615 * transmitted before switching the 485 transceiver to
618 * The txfifo might have been refilled by putchar() while
619 * we were waiting for the transmission complete interrupt.
620 * In this case, we must restart the UDR empty interrupt,
621 * otherwise we'd stop the serial port with some data
622 * still pending in the buffer.
624 SIGNAL(SIG_UART0_TRANS)
628 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
629 if (fifo_isempty(txfifo))
632 UARTDescs[SER_UART0].sending = false;
635 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
639 #endif /* SER_UART0_BUS_TXOFF */
645 * Serial 1 TX interrupt handler
647 SIGNAL(SIG_UART1_DATA)
651 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
653 if (fifo_isempty(txfifo))
656 #ifndef SER_UART1_BUS_TXOFF
657 UARTDescs[SER_UART1].sending = false;
660 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
663 // Disable rx interrupt and tx, enable CTS interrupt
665 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
666 sbi(EIFR, EIMSKB_CTS);
667 sbi(EIMSK, EIMSKB_CTS);
672 char c = fifo_pop(txfifo);
673 SER_UART1_BUS_TXCHAR(c);
679 #ifdef SER_UART1_BUS_TXOFF
681 * Serial port 1 TX complete interrupt handler.
683 * \sa port 0 TX complete handler.
685 SIGNAL(SIG_UART1_TRANS)
689 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
690 if (fifo_isempty(txfifo))
693 UARTDescs[SER_UART1].sending = false;
696 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
700 #endif /* SER_UART1_BUS_TXOFF */
702 #endif // AVR_HAS_UART1
706 * Serial 0 RX complete interrupt handler.
708 * This handler is interruptible.
709 * Interrupt are re-enabled as soon as recv complete interrupt is
710 * disabled. Using INTERRUPT() is troublesome when the serial
711 * is heavily loaded, because an interrupt could be retriggered
712 * when executing the handler prologue before RXCIE is disabled.
714 * \note The code that re-enables interrupts is commented out
715 * because in some nasty cases the interrupt is retriggered.
716 * This is probably due to the RXC flag being set before
717 * RXCIE is cleared. Unfortunately the RXC flag is read-only
718 * and can't be cleared by code.
720 SIGNAL(SIG_UART0_RECV)
724 /* Disable Recv complete IRQ */
725 //UCSR0B &= ~BV(RXCIE);
728 /* Should be read before UDR */
729 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
731 /* To clear the RXC flag we must _always_ read the UDR even when we're
732 * not going to accept the incoming data, otherwise a new interrupt
733 * will occur once the handler terminates.
736 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
738 if (fifo_isfull(rxfifo))
739 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
742 fifo_push(rxfifo, c);
743 #if CONFIG_SER_HWHANDSHAKE
744 if (fifo_isfull(rxfifo))
749 /* Re-enable receive complete int */
751 //UCSR0B |= BV(RXCIE);
760 * Serial 1 RX complete interrupt handler.
762 * This handler is interruptible.
763 * Interrupt are re-enabled as soon as recv complete interrupt is
764 * disabled. Using INTERRUPT() is troublesome when the serial
765 * is heavily loaded, because an interrupt could be retriggered
766 * when executing the handler prologue before RXCIE is disabled.
768 * \see SIGNAL(SIG_UART0_RECV)
770 SIGNAL(SIG_UART1_RECV)
774 /* Disable Recv complete IRQ */
775 //UCSR1B &= ~BV(RXCIE);
778 /* Should be read before UDR */
779 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
781 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
782 * not going to accept the incoming data
785 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
786 //ASSERT_VALID_FIFO(rxfifo);
788 if (UNLIKELY(fifo_isfull(rxfifo)))
789 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
792 fifo_push(rxfifo, c);
793 #if CONFIG_SER_HWHANDSHAKE
794 if (fifo_isfull(rxfifo))
798 /* Re-enable receive complete int */
799 //UCSR1B |= BV(RXCIE);
804 #endif // AVR_HAS_UART1
808 * SPI interrupt handler
812 /* Read incoming byte. */
813 if (!fifo_isfull(&ser_spi->rxfifo))
814 fifo_push(&ser_spi->rxfifo, SPDR);
818 ser_spi->status |= SERRF_RXFIFOOVERRUN;
822 if (!fifo_isempty(&ser_spi->txfifo))
823 SPDR = fifo_pop(&ser_spi->txfifo);
825 UARTDescs[SER_SPI].sending = false;