4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.23 2005/01/11 18:09:07 aleph
42 *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
44 *#* Revision 1.22 2004/12/31 17:47:45 bernie
45 *#* Rename UNUSED() to UNUSED_ARG().
47 *#* Revision 1.21 2004/12/13 12:07:06 bernie
48 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
50 *#* Revision 1.20 2004/12/13 11:51:43 bernie
51 *#* Fix a latent bug with reentrant serial IRQs.
53 *#* Revision 1.19 2004/12/13 11:51:08 bernie
54 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
56 *#* Revision 1.18 2004/12/08 08:03:48 bernie
59 *#* Revision 1.17 2004/10/19 07:52:35 bernie
60 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
62 *#* Revision 1.16 2004/10/03 18:45:48 bernie
63 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
65 *#* Revision 1.15 2004/09/14 21:05:36 bernie
66 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
68 *#* Revision 1.14 2004/09/06 21:50:00 bernie
71 *#* Revision 1.13 2004/09/06 21:40:50 bernie
72 *#* Move buffer handling in chip-specific driver.
74 *#* Revision 1.12 2004/08/29 22:06:10 bernie
75 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
77 *#* Revision 1.10 2004/08/10 06:30:41 bernie
78 *#* Major redesign of serial bus policy handling.
80 *#* Revision 1.9 2004/08/02 20:20:29 aleph
81 *#* Merge from project_ks
83 *#* Revision 1.8 2004/07/29 22:57:09 bernie
84 *#* Several tweaks to reduce code size on ATmega8.
86 *#* Revision 1.7 2004/07/18 21:54:23 bernie
87 *#* Add ATmega8 support.
89 *#* Revision 1.5 2004/06/27 15:25:40 aleph
90 *#* Add missing callbacks for SPI;
91 *#* Change UNUSED() macro to new version with two args;
92 *#* Use TX line filling only on the correct KBUS serial port;
93 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
95 *#* Revision 1.4 2004/06/03 11:27:09 bernie
96 *#* Add dual-license information.
98 *#* Revision 1.3 2004/06/02 21:35:24 aleph
99 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
101 *#* Revision 1.2 2004/05/23 18:21:53 bernie
102 *#* Trim CVS logs and cleanup header info.
109 #include "hw.h" /* Required for bus macros overrides */
112 #include <drv/timer.h>
113 #include <mware/fifobuf.h>
115 #include <avr/signal.h>
120 * \name Hardware handshake (RTS/CTS).
124 #define RTS_ON do {} while (0)
127 #define RTS_OFF do {} while (0)
130 #define IS_CTS_ON true
133 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
139 * \name Overridable serial bus hooks
141 * These can be redefined in hw.h to implement
142 * special bus policies such as half-duplex, 485, etc.
146 * TXBEGIN TXCHAR TXEND TXOFF
147 * | __________|__________ | |
150 * ______ __ __ __ __ __ __ ________________
151 * \/ \/ \/ \/ \/ \/ \/
152 * ______/\__/\__/\__/\__/\__/\__/
158 #ifndef SER_UART0_BUS_TXINIT
160 * Default TXINIT macro - invoked in uart0_init()
162 * - Enable both the receiver and the transmitter
163 * - Enable only the RX complete interrupt
165 #define SER_UART0_BUS_TXINIT do { \
166 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
170 #ifndef SER_UART0_BUS_TXBEGIN
172 * Invoked before starting a transmission
174 * - Enable both the receiver and the transmitter
175 * - Enable both the RX complete and UDR empty interrupts
177 #define SER_UART0_BUS_TXBEGIN do { \
178 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
182 #ifndef SER_UART0_BUS_TXCHAR
184 * Invoked to send one character.
186 #define SER_UART0_BUS_TXCHAR(c) do { \
191 #ifndef SER_UART0_BUS_TXEND
193 * Invoked as soon as the txfifo becomes empty
195 * - Keep both the receiver and the transmitter enabled
196 * - Keep the RX complete interrupt enabled
197 * - Disable the UDR empty interrupt
199 #define SER_UART0_BUS_TXEND do { \
200 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
204 #ifndef SER_UART0_BUS_TXOFF
206 * \def SER_UART0_BUS_TXOFF
208 * Invoked after the last character has been transmitted
210 * The default is no action.
213 #define SER_UART0_BUS_TXOFF
217 #ifndef SER_UART1_BUS_TXINIT
218 /*! \sa SER_UART0_BUS_TXINIT */
219 #define SER_UART1_BUS_TXINIT do { \
220 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
223 #ifndef SER_UART1_BUS_TXBEGIN
224 /*! \sa SER_UART0_BUS_TXBEGIN */
225 #define SER_UART1_BUS_TXBEGIN do { \
226 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
229 #ifndef SER_UART1_BUS_TXCHAR
230 /*! \sa SER_UART0_BUS_TXCHAR */
231 #define SER_UART1_BUS_TXCHAR(c) do { \
235 #ifndef SER_UART1_BUS_TXEND
236 /*! \sa SER_UART0_BUS_TXEND */
237 #define SER_UART1_BUS_TXEND do { \
238 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
241 #ifndef SER_UART1_BUS_TXOFF
243 * \def SER_UART1_BUS_TXOFF
245 * \see SER_UART0_BUS_TXOFF
248 #define SER_UART1_BUS_TXOFF
254 /* SPI port and pin configuration */
255 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
256 #define SPI_PORT PORTB
258 #define SPI_SCK_BIT PB1
259 #define SPI_MOSI_BIT PB2
260 #define SPI_MISO_BIT PB3
261 #elif CPU_AVR_ATMEGA8
262 #define SPI_PORT PORTB
264 #define SPI_SCK_BIT PB5
265 #define SPI_MOSI_BIT PB3
266 #define SPI_MISO_BIT PB4
268 #error Unknown architecture
271 /* USART register definitions */
272 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
273 #define AVR_HAS_UART1 1
274 #elif CPU_AVR_ATMEGA8
275 #define AVR_HAS_UART1 0
282 #define SIG_UART0_DATA SIG_UART_DATA
283 #define SIG_UART0_RECV SIG_UART_RECV
284 #define SIG_UART0_TRANS SIG_UART_TRANS
285 #elif CPU_AVR_ATMEGA103
286 #define AVR_HAS_UART1 0
291 #define SIG_UART0_DATA SIG_UART_DATA
292 #define SIG_UART0_RECV SIG_UART_RECV
293 #define SIG_UART0_TRANS SIG_UART_TRANS
295 #error Unknown architecture
300 * \def CONFIG_SER_STROBE
302 * This is a debug facility that can be used to
303 * monitor SER interrupt activity on an external pin.
305 * To use strobes, redefine the macros SER_STROBE_ON,
306 * SER_STROBE_OFF and SER_STROBE_INIT and set
307 * CONFIG_SER_STROBE to 1.
309 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
310 #define SER_STROBE_ON do {/*nop*/} while(0)
311 #define SER_STROBE_OFF do {/*nop*/} while(0)
312 #define SER_STROBE_INIT do {/*nop*/} while(0)
316 /* From the high-level serial driver */
317 extern struct Serial ser_handles[SER_CNT];
319 /* TX and RX buffers */
320 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
321 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
323 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
324 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
326 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
327 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
331 * Internal hardware state structure
333 * The \a sending variable is true while the transmission
334 * interrupt is retriggering itself.
336 * For the USARTs the \a sending flag is useful for taking specific
337 * actions before sending a burst of data, at the start of a trasmission
338 * but not before every char sent.
340 * For the SPI, this flag is necessary because the SPI sends and receives
341 * bytes at the same time and the SPI IRQ is unique for send/receive.
342 * The only way to start transmission is to write data in SPDR (this
343 * is done by spi_starttx()). We do this *only* if a transfer is
344 * not already started.
348 struct SerialHardware hw;
349 volatile bool sending;
354 * These are to trick GCC into *not* using absolute addressing mode
355 * when accessing ser_handles, which is very expensive.
357 * Accessing through these pointers generates much shorter
358 * (and hopefully faster) code.
360 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
362 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
364 struct Serial *ser_spi = &ser_handles[SER_SPI];
371 static void uart0_init(
372 UNUSED_ARG(struct SerialHardware *, _hw),
373 UNUSED_ARG(struct Serial *, ser))
375 SER_UART0_BUS_TXINIT;
380 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
385 static void uart0_enabletxirq(struct SerialHardware *_hw)
387 struct AvrSerial *hw = (struct AvrSerial *)_hw;
390 * WARNING: racy code here! The tx interrupt sets hw->sending to false
391 * when it runs with an empty fifo. The order of statements in the
397 SER_UART0_BUS_TXBEGIN;
401 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
403 /* Compute baud-rate period */
404 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
406 #ifndef __AVR_ATmega103__
407 UBRR0H = (period) >> 8;
411 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
414 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
416 #if !CPU_AVR_ATMEGA103
417 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
423 static void uart1_init(
424 UNUSED_ARG(struct SerialHardware *, _hw),
425 UNUSED_ARG(struct Serial *, ser))
427 SER_UART1_BUS_TXINIT;
432 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
437 static void uart1_enabletxirq(struct SerialHardware *_hw)
439 struct AvrSerial *hw = (struct AvrSerial *)_hw;
442 * WARNING: racy code here! The tx interrupt
443 * sets hw->sending to false when it runs with
444 * an empty fifo. The order of the statements
445 * in the if-block matters.
450 SER_UART1_BUS_TXBEGIN;
454 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
456 /* Compute baud-rate period */
457 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
459 UBRR1H = (period) >> 8;
462 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
465 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
467 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
470 #endif // AVR_HAS_UART1
472 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
475 * Set MOSI and SCK ports out, MISO in.
477 * The ATmega64/128 datasheet explicitly states that the input/output
478 * state of the SPI pins is not significant, as when the SPI is
479 * active the I/O port are overrided.
480 * This is *blatantly FALSE*.
482 * Moreover, the MISO pin on the board_kc *must* be in high impedance
483 * state even when the SPI is off, because the line is wired together
484 * with the KBus serial RX, and the transmitter of the slave boards
485 * would be unable to drive the line.
487 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
488 SPI_DDR &= ~BV(SPI_MISO_BIT);
489 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
490 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
495 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
498 /* Set all pins as inputs */
499 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
502 static void spi_starttx(struct SerialHardware *_hw)
504 struct AvrSerial *hw = (struct AvrSerial *)_hw;
507 IRQ_SAVE_DISABLE(flags);
509 /* Send data only if the SPI is not already transmitting */
510 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
513 SPDR = fifo_pop(&ser_spi->txfifo);
519 static void spi_setbaudrate(
520 UNUSED_ARG(struct SerialHardware *, _hw),
521 UNUSED_ARG(unsigned long, rate))
526 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
532 // FIXME: move into compiler.h? Ditch?
534 #define C99INIT(name,val) .name = val
535 #elif defined(__GNUC__)
536 #define C99INIT(name,val) name: val
538 #warning No designated initializers, double check your code
539 #define C99INIT(name,val) (val)
543 * High-level interface data structures
545 static const struct SerialHardwareVT UART0_VT =
547 C99INIT(init, uart0_init),
548 C99INIT(cleanup, uart0_cleanup),
549 C99INIT(setbaudrate, uart0_setbaudrate),
550 C99INIT(setparity, uart0_setparity),
551 C99INIT(enabletxirq, uart0_enabletxirq),
555 static const struct SerialHardwareVT UART1_VT =
557 C99INIT(init, uart1_init),
558 C99INIT(cleanup, uart1_cleanup),
559 C99INIT(setbaudrate, uart1_setbaudrate),
560 C99INIT(setparity, uart1_setparity),
561 C99INIT(enabletxirq, uart1_enabletxirq),
563 #endif // AVR_HAS_UART1
565 static const struct SerialHardwareVT SPI_VT =
567 C99INIT(init, spi_init),
568 C99INIT(cleanup, spi_cleanup),
569 C99INIT(setbaudrate, spi_setbaudrate),
570 C99INIT(setparity, spi_setparity),
571 C99INIT(enabletxirq, spi_starttx),
574 static struct AvrSerial UARTDescs[SER_CNT] =
578 C99INIT(table, &UART0_VT),
579 C99INIT(txbuffer, uart0_txbuffer),
580 C99INIT(rxbuffer, uart0_rxbuffer),
581 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
582 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
584 C99INIT(sending, false),
589 C99INIT(table, &UART1_VT),
590 C99INIT(txbuffer, uart1_txbuffer),
591 C99INIT(rxbuffer, uart1_rxbuffer),
592 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
593 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
595 C99INIT(sending, false),
600 C99INIT(table, &SPI_VT),
601 C99INIT(txbuffer, spi_txbuffer),
602 C99INIT(rxbuffer, spi_rxbuffer),
603 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
604 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
606 C99INIT(sending, false),
610 struct SerialHardware* ser_hw_getdesc(int unit)
612 ASSERT(unit < SER_CNT);
613 return &UARTDescs[unit].hw;
621 #if CONFIG_SER_HWHANDSHAKE
623 //! This interrupt is triggered when the CTS line goes high
626 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
627 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
628 cbi(EIMSK, EIMSKB_CTS);
631 #endif // CONFIG_SER_HWHANDSHAKE
635 * Serial 0 TX interrupt handler
637 SIGNAL(SIG_UART0_DATA)
641 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
643 if (fifo_isempty(txfifo))
646 #ifndef SER_UART0_BUS_TXOFF
647 UARTDescs[SER_UART0].sending = false;
650 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
653 // Disable rx interrupt and tx, enable CTS interrupt
655 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
656 sbi(EIFR, EIMSKB_CTS);
657 sbi(EIMSK, EIMSKB_CTS);
662 char c = fifo_pop(txfifo);
663 SER_UART0_BUS_TXCHAR(c);
669 #ifdef SER_UART0_BUS_TXOFF
671 * Serial port 0 TX complete interrupt handler.
673 * This IRQ is usually disabled. The UDR-empty interrupt
674 * enables it when there's no more data to transmit.
675 * We need to wait until the last character has been
676 * transmitted before switching the 485 transceiver to
679 * The txfifo might have been refilled by putchar() while
680 * we were waiting for the transmission complete interrupt.
681 * In this case, we must restart the UDR empty interrupt,
682 * otherwise we'd stop the serial port with some data
683 * still pending in the buffer.
685 SIGNAL(SIG_UART0_TRANS)
689 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
690 if (fifo_isempty(txfifo))
693 UARTDescs[SER_UART0].sending = false;
696 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
700 #endif /* SER_UART0_BUS_TXOFF */
706 * Serial 1 TX interrupt handler
708 SIGNAL(SIG_UART1_DATA)
712 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
714 if (fifo_isempty(txfifo))
717 #ifndef SER_UART1_BUS_TXOFF
718 UARTDescs[SER_UART1].sending = false;
721 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
724 // Disable rx interrupt and tx, enable CTS interrupt
726 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
727 sbi(EIFR, EIMSKB_CTS);
728 sbi(EIMSK, EIMSKB_CTS);
733 char c = fifo_pop(txfifo);
734 SER_UART1_BUS_TXCHAR(c);
740 #ifdef SER_UART1_BUS_TXOFF
742 * Serial port 1 TX complete interrupt handler.
744 * \sa port 0 TX complete handler.
746 SIGNAL(SIG_UART1_TRANS)
750 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
751 if (fifo_isempty(txfifo))
754 UARTDescs[SER_UART1].sending = false;
757 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
761 #endif /* SER_UART1_BUS_TXOFF */
763 #endif // AVR_HAS_UART1
767 * Serial 0 RX complete interrupt handler.
769 * This handler is interruptible.
770 * Interrupt are reenabled as soon as recv complete interrupt is
771 * disabled. Using INTERRUPT() is troublesome when the serial
772 * is heavily loaded, because an interrupt could be retriggered
773 * when executing the handler prologue before RXCIE is disabled.
775 * \note The code that re-enables interrupts is commented out
776 * because in some nasty cases the interrupt is retriggered.
777 * This is probably due to the RXC flag being set before
778 * RXCIE is cleared. Unfortunately the RXC flag is read-only
779 * and can't be cleared by code.
781 SIGNAL(SIG_UART0_RECV)
785 /* Disable Recv complete IRQ */
786 //UCSR0B &= ~BV(RXCIE);
789 /* Should be read before UDR */
790 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
792 /* To clear the RXC flag we must _always_ read the UDR even when we're
793 * not going to accept the incoming data, otherwise a new interrupt
794 * will occur once the handler terminates.
797 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
799 if (fifo_isfull(rxfifo))
800 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
803 fifo_push(rxfifo, c);
804 #if CONFIG_SER_HWHANDSHAKE
805 if (fifo_isfull(rxfifo))
810 /* Reenable receive complete int */
812 //UCSR0B |= BV(RXCIE);
821 * Serial 1 RX complete interrupt handler.
823 * This handler is interruptible.
824 * Interrupt are reenabled as soon as recv complete interrupt is
825 * disabled. Using INTERRUPT() is troublesome when the serial
826 * is heavily loaded, because an interrupt could be retriggered
827 * when executing the handler prologue before RXCIE is disabled.
829 * \see SIGNAL(SIG_UART0_RECV)
831 SIGNAL(SIG_UART1_RECV)
835 /* Disable Recv complete IRQ */
836 //UCSR1B &= ~BV(RXCIE);
839 /* Should be read before UDR */
840 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
842 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
843 * not going to accept the incoming data
846 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
847 //ASSERT_VALID_FIFO(rxfifo);
849 if (UNLIKELY(fifo_isfull(rxfifo)))
850 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
853 fifo_push(rxfifo, c);
854 #if CONFIG_SER_HWHANDSHAKE
855 if (fifo_isfull(rxfifo))
859 /* Re-enable receive complete int */
861 //UCSR1B |= BV(RXCIE);
866 #endif // AVR_HAS_UART1
870 * SPI interrupt handler
876 /* Read incoming byte. */
877 if (!fifo_isfull(&ser_spi->rxfifo))
878 fifo_push(&ser_spi->rxfifo, SPDR);
882 ser_spi->status |= SERRF_RXFIFOOVERRUN;
886 if (!fifo_isempty(&ser_spi->txfifo))
887 SPDR = fifo_pop(&ser_spi->txfifo);
889 UARTDescs[SER_SPI].sending = false;