4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.19 2004/12/13 11:51:08 bernie
42 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
44 *#* Revision 1.18 2004/12/08 08:03:48 bernie
47 *#* Revision 1.17 2004/10/19 07:52:35 bernie
48 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
50 *#* Revision 1.16 2004/10/03 18:45:48 bernie
51 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
53 *#* Revision 1.15 2004/09/14 21:05:36 bernie
54 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
56 *#* Revision 1.14 2004/09/06 21:50:00 bernie
59 *#* Revision 1.13 2004/09/06 21:40:50 bernie
60 *#* Move buffer handling in chip-specific driver.
62 *#* Revision 1.12 2004/08/29 22:06:10 bernie
63 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
65 *#* Revision 1.10 2004/08/10 06:30:41 bernie
66 *#* Major redesign of serial bus policy handling.
68 *#* Revision 1.9 2004/08/02 20:20:29 aleph
69 *#* Merge from project_ks
71 *#* Revision 1.8 2004/07/29 22:57:09 bernie
72 *#* Several tweaks to reduce code size on ATmega8.
74 *#* Revision 1.7 2004/07/18 21:54:23 bernie
75 *#* Add ATmega8 support.
77 *#* Revision 1.5 2004/06/27 15:25:40 aleph
78 *#* Add missing callbacks for SPI;
79 *#* Change UNUSED() macro to new version with two args;
80 *#* Use TX line filling only on the correct KBUS serial port;
81 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
83 *#* Revision 1.4 2004/06/03 11:27:09 bernie
84 *#* Add dual-license information.
86 *#* Revision 1.3 2004/06/02 21:35:24 aleph
87 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
89 *#* Revision 1.2 2004/05/23 18:21:53 bernie
90 *#* Trim CVS logs and cleanup header info.
97 #include "hw.h" /* Required for bus macros overrides */
100 #include <drv/timer.h>
101 #include <mware/fifobuf.h>
103 #include <avr/signal.h>
108 * \name Hardware handshake (RTS/CTS).
112 #define RTS_ON do {} while (0)
115 #define RTS_OFF do {} while (0)
118 #define IS_CTS_ON true
121 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
127 * \name Overridable serial bus hooks
129 * These can be redefined in hw.h to implement
130 * special bus policies such as half-duplex, 485, etc.
134 * TXBEGIN TXCHAR TXEND TXOFF
135 * | __________|__________ | |
138 * ______ __ __ __ __ __ __ ________________
139 * \/ \/ \/ \/ \/ \/ \/
140 * ______/\__/\__/\__/\__/\__/\__/
146 #ifndef SER_UART0_BUS_TXINIT
148 * Default TXINIT macro - invoked in uart0_init()
150 * - Enable both the receiver and the transmitter
151 * - Enable only the RX complete interrupt
153 #define SER_UART0_BUS_TXINIT do { \
154 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
158 #ifndef SER_UART0_BUS_TXBEGIN
160 * Invoked before starting a transmission
162 * - Enable both the receiver and the transmitter
163 * - Enable both the RX complete and UDR empty interrupts
165 #define SER_UART0_BUS_TXBEGIN do { \
166 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
170 #ifndef SER_UART0_BUS_TXCHAR
172 * Invoked to send one character.
174 #define SER_UART0_BUS_TXCHAR(c) do { \
179 #ifndef SER_UART0_BUS_TXEND
181 * Invoked as soon as the txfifo becomes empty
183 * - Keep both the receiver and the transmitter enabled
184 * - Keep the RX complete interrupt enabled
185 * - Disable the UDR empty interrupt
187 #define SER_UART0_BUS_TXEND do { \
188 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
192 #ifndef SER_UART0_BUS_TXOFF
194 * \def SER_UART0_BUS_TXOFF
196 * Invoked after the last character has been transmitted
198 * The default is no action.
201 #define SER_UART0_BUS_TXOFF
205 #ifndef SER_UART1_BUS_TXINIT
206 /*! \sa SER_UART0_BUS_TXINIT */
207 #define SER_UART1_BUS_TXINIT do { \
208 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
211 #ifndef SER_UART1_BUS_TXBEGIN
212 /*! \sa SER_UART0_BUS_TXBEGIN */
213 #define SER_UART1_BUS_TXBEGIN do { \
214 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
217 #ifndef SER_UART1_BUS_TXCHAR
218 /*! \sa SER_UART0_BUS_TXCHAR */
219 #define SER_UART1_BUS_TXCHAR(c) do { \
223 #ifndef SER_UART1_BUS_TXEND
224 /*! \sa SER_UART0_BUS_TXEND */
225 #define SER_UART1_BUS_TXEND do { \
226 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
229 #ifndef SER_UART1_BUS_TXOFF
231 * \def SER_UART1_BUS_TXOFF
233 * \see SER_UART0_BUS_TXOFF
236 #define SER_UART1_BUS_TXOFF
242 /* SPI port and pin configuration */
243 #define SPI_PORT PORTB
245 #define SPI_SCK_BIT PB1
246 #define SPI_MOSI_BIT PB2
247 #define SPI_MISO_BIT PB3
249 /* USART register definitions */
250 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
251 #define AVR_HAS_UART1 1
252 #elif CPU_AVR_ATMEGA8
253 #define AVR_HAS_UART1 0
260 #define SIG_UART0_DATA SIG_UART_DATA
261 #define SIG_UART0_RECV SIG_UART_RECV
262 #elif CPU_AVR_ATMEGA103
263 #define AVR_HAS_UART1 0
268 #define SIG_UART0_DATA SIG_UART_DATA
269 #define SIG_UART0_RECV SIG_UART_RECV
271 #error Unknown architecture
276 * \def CONFIG_SER_STROBE
278 * This is a debug facility that can be used to
279 * monitor SER interrupt activity on an external pin.
281 * To use strobes, redefine the macros SER_STROBE_ON,
282 * SER_STROBE_OFF and SER_STROBE_INIT and set
283 * CONFIG_SER_STROBE to 1.
285 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
286 #define SER_STROBE_ON do {/*nop*/} while(0)
287 #define SER_STROBE_OFF do {/*nop*/} while(0)
288 #define SER_STROBE_INIT do {/*nop*/} while(0)
292 /* From the high-level serial driver */
293 extern struct Serial ser_handles[SER_CNT];
295 /* TX and RX buffers */
296 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
297 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
299 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
300 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
302 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
303 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
307 * Internal hardware state structure
309 * The \a sending variable is true while the transmission
310 * interrupt is retriggering itself.
312 * For the USARTs the \a sending flag is useful for taking specific
313 * actions before sending a burst of data, at the start of a trasmission
314 * but not before every char sent.
316 * For the SPI, this flag is necessary because the SPI sends and receives
317 * bytes at the same time and the SPI IRQ is unique for send/receive.
318 * The only way to start transmission is to write data in SPDR (this
319 * is done by spi_starttx()). We do this *only* if a transfer is
320 * not already started.
324 struct SerialHardware hw;
325 volatile bool sending;
330 * These are to trick GCC into *not* using absolute addressing mode
331 * when accessing ser_handles, which is very expensive.
333 * Accessing through these pointers generates much shorter
334 * (and hopefully faster) code.
336 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
338 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
340 struct Serial *ser_spi = &ser_handles[SER_SPI];
347 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
349 SER_UART0_BUS_TXINIT;
353 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
358 static void uart0_enabletxirq(struct SerialHardware *_hw)
360 struct AvrSerial *hw = (struct AvrSerial *)_hw;
363 * WARNING: racy code here! The tx interrupt sets hw->sending to false
364 * when it runs with an empty fifo. The order of statements in the
370 SER_UART0_BUS_TXBEGIN;
374 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
376 /* Compute baud-rate period */
377 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
379 #ifndef __AVR_ATmega103__
380 UBRR0H = (period) >> 8;
384 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
387 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
389 #if !CPU_AVR_ATMEGA103
390 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
396 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
398 SER_UART1_BUS_TXINIT;
403 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
408 static void uart1_enabletxirq(struct SerialHardware *_hw)
410 struct AvrSerial *hw = (struct AvrSerial *)_hw;
413 * WARNING: racy code here! The tx interrupt
414 * sets hw->sending to false when it runs with
415 * an empty fifo. The order of the statements
416 * in the if-block matters.
421 SER_UART1_BUS_TXBEGIN;
425 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
427 /* Compute baud-rate period */
428 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
430 UBRR1H = (period) >> 8;
433 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
436 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
438 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
441 #endif // AVR_HAS_UART1
443 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
446 * Set MOSI and SCK ports out, MISO in.
448 * The ATmega64/128 datasheet explicitly states that the input/output
449 * state of the SPI pins is not significant, as when the SPI is
450 * active the I/O port are overrided.
451 * This is *blatantly FALSE*.
453 * Moreover, the MISO pin on the board_kc *must* be in high impedance
454 * state even when the SPI is off, because the line is wired together
455 * with the KBus serial RX, and the transmitter of the slave boards
456 * would be unable to drive the line.
458 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
459 SPI_DDR &= ~BV(SPI_MISO_BIT);
460 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
461 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
464 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
467 /* Set all pins as inputs */
468 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
471 static void spi_starttx(struct SerialHardware *_hw)
473 struct AvrSerial *hw = (struct AvrSerial *)_hw;
476 DISABLE_IRQSAVE(flags);
478 /* Send data only if the SPI is not already transmitting */
479 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
482 SPDR = fifo_pop(&ser_spi->txfifo);
485 ENABLE_IRQRESTORE(flags);
488 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
493 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
499 // FIXME: move into compiler.h? Ditch?
501 #define C99INIT(name,val) .name = val
502 #elif defined(__GNUC__)
503 #define C99INIT(name,val) name: val
505 #warning No designated initializers, double check your code
506 #define C99INIT(name,val) (val)
510 * High-level interface data structures
512 static const struct SerialHardwareVT UART0_VT =
514 C99INIT(init, uart0_init),
515 C99INIT(cleanup, uart0_cleanup),
516 C99INIT(setbaudrate, uart0_setbaudrate),
517 C99INIT(setparity, uart0_setparity),
518 C99INIT(enabletxirq, uart0_enabletxirq),
522 static const struct SerialHardwareVT UART1_VT =
524 C99INIT(init, uart1_init),
525 C99INIT(cleanup, uart1_cleanup),
526 C99INIT(setbaudrate, uart1_setbaudrate),
527 C99INIT(setparity, uart1_setparity),
528 C99INIT(enabletxirq, uart1_enabletxirq),
530 #endif // AVR_HAS_UART1
532 static const struct SerialHardwareVT SPI_VT =
534 C99INIT(init, spi_init),
535 C99INIT(cleanup, spi_cleanup),
536 C99INIT(setbaudrate, spi_setbaudrate),
537 C99INIT(setparity, spi_setparity),
538 C99INIT(enabletxirq, spi_starttx),
541 static struct AvrSerial UARTDescs[SER_CNT] =
545 C99INIT(table, &UART0_VT),
546 C99INIT(txbuffer, uart0_txbuffer),
547 C99INIT(rxbuffer, uart0_rxbuffer),
548 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
549 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
551 C99INIT(sending, false),
556 C99INIT(table, &UART1_VT),
557 C99INIT(txbuffer, uart1_txbuffer),
558 C99INIT(rxbuffer, uart1_rxbuffer),
559 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
560 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
562 C99INIT(sending, false),
567 C99INIT(table, &SPI_VT),
568 C99INIT(txbuffer, spi_txbuffer),
569 C99INIT(rxbuffer, spi_rxbuffer),
570 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
571 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
573 C99INIT(sending, false),
577 struct SerialHardware* ser_hw_getdesc(int unit)
579 ASSERT(unit < SER_CNT);
580 return &UARTDescs[unit].hw;
588 #if CONFIG_SER_HWHANDSHAKE
590 //! This interrupt is triggered when the CTS line goes high
593 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
594 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
595 cbi(EIMSK, EIMSKB_CTS);
598 #endif // CONFIG_SER_HWHANDSHAKE
602 * Serial 0 TX interrupt handler
604 SIGNAL(SIG_UART0_DATA)
608 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
610 if (fifo_isempty(txfifo))
613 #ifndef SER_UART0_BUS_TXOFF
614 UARTDescs[SER_UART0].sending = false;
617 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
620 // Disable rx interrupt and tx, enable CTS interrupt
622 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
623 sbi(EIFR, EIMSKB_CTS);
624 sbi(EIMSK, EIMSKB_CTS);
629 char c = fifo_pop(txfifo);
630 SER_UART0_BUS_TXCHAR(c);
636 #ifdef SER_UART0_BUS_TXOFF
638 * Serial port 0 TX complete interrupt handler.
640 * This IRQ is usually disabled. The UDR-empty interrupt
641 * enables it when there's no more data to transmit.
642 * We need to wait until the last character has been
643 * transmitted before switching the 485 transceiver to
646 * The txfifo might have been refilled by putchar() while
647 * we were waiting for the transmission complete interrupt.
648 * In this case, we must restart the UDR empty interrupt,
649 * otherwise we'd stop the serial port with some data
650 * still pending in the buffer.
652 SIGNAL(SIG_UART0_TRANS)
656 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
657 if (fifo_isempty(txfifo))
660 UARTDescs[SER_UART0].sending = false;
663 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
667 #endif /* SER_UART0_BUS_TXOFF */
673 * Serial 1 TX interrupt handler
675 SIGNAL(SIG_UART1_DATA)
679 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
681 if (fifo_isempty(txfifo))
684 #ifndef SER_UART1_BUS_TXOFF
685 UARTDescs[SER_UART1].sending = false;
688 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
691 // Disable rx interrupt and tx, enable CTS interrupt
693 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
694 sbi(EIFR, EIMSKB_CTS);
695 sbi(EIMSK, EIMSKB_CTS);
700 char c = fifo_pop(txfifo);
701 SER_UART1_BUS_TXCHAR(c);
707 #ifdef SER_UART1_BUS_TXOFF
709 * Serial port 1 TX complete interrupt handler.
711 * \sa port 0 TX complete handler.
713 SIGNAL(SIG_UART1_TRANS)
717 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
718 if (fifo_isempty(txfifo))
721 UARTDescs[SER_UART1].sending = false;
724 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
728 #endif /* SER_UART1_BUS_TXOFF */
730 #endif // AVR_HAS_UART1
734 * Serial 0 RX complete interrupt handler.
736 * This handler is interruptible.
737 * Interrupt are reenabled as soon as recv complete interrupt is
738 * disabled. Using INTERRUPT() is troublesome when the serial
739 * is heavily loaded, because an interrupt could be retriggered
740 * when executing the handler prologue before RXCIE is disabled.
742 * \note The code that re-enables interrupts is commented out
743 * because in some nasty cases the interrupt is retriggered.
744 * This is probably due to the RXC flag being set before
745 * RXCIE is cleared. Unfortunately the RXC flag is read-only
746 * and can't be cleared by code.
748 SIGNAL(SIG_UART0_RECV)
752 /* Disable Recv complete IRQ */
753 //UCSR0B &= ~BV(RXCIE);
756 /* Should be read before UDR */
757 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
759 /* To clear the RXC flag we must _always_ read the UDR even when we're
760 * not going to accept the incoming data, otherwise a new interrupt
761 * will occur once the handler terminates.
764 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
766 if (fifo_isfull(rxfifo))
767 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
770 fifo_push(rxfifo, c);
771 #if CONFIG_SER_HWHANDSHAKE
772 if (fifo_isfull(rxfifo))
777 /* Reenable receive complete int */
779 //UCSR0B |= BV(RXCIE);
788 * Serial 1 RX complete interrupt handler.
790 * This handler is interruptible.
791 * Interrupt are reenabled as soon as recv complete interrupt is
792 * disabled. Using INTERRUPT() is troublesome when the serial
793 * is heavily loaded, because an interrupt could be retriggered
794 * when executing the handler prologue before RXCIE is disabled.
796 * \see SIGNAL(SIG_UART0_RECV)
798 SIGNAL(SIG_UART1_RECV)
802 /* Disable Recv complete IRQ */
803 //UCSR1B &= ~BV(RXCIE);
806 /* Should be read before UDR */
807 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
809 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
810 * not going to accept the incoming data
813 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
814 //ASSERT_VALID_FIFO(rxfifo);
816 if (UNLIKELY(fifo_isfull(rxfifo)))
817 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
820 fifo_push(rxfifo, c);
821 #if CONFIG_SER_HWHANDSHAKE
822 if (fifo_isfull(rxfifo))
826 /* Re-enable receive complete int */
827 //UCSR1B |= BV(RXCIE);
832 #endif // AVR_HAS_UART1
836 * SPI interrupt handler
840 /* Read incoming byte. */
841 if (!fifo_isfull(&ser_spi->rxfifo))
842 fifo_push(&ser_spi->rxfifo, SPDR);
846 ser_spi->status |= SERRF_RXFIFOOVERRUN;
850 if (!fifo_isempty(&ser_spi->txfifo))
851 SPDR = fifo_pop(&ser_spi->txfifo);
853 UARTDescs[SER_SPI].sending = false;