4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.21 2004/12/13 12:07:06 bernie
42 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
44 *#* Revision 1.20 2004/12/13 11:51:43 bernie
45 *#* Fix a latent bug with reentrant serial IRQs.
47 *#* Revision 1.19 2004/12/13 11:51:08 bernie
48 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
50 *#* Revision 1.18 2004/12/08 08:03:48 bernie
53 *#* Revision 1.17 2004/10/19 07:52:35 bernie
54 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
56 *#* Revision 1.16 2004/10/03 18:45:48 bernie
57 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
59 *#* Revision 1.15 2004/09/14 21:05:36 bernie
60 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
62 *#* Revision 1.14 2004/09/06 21:50:00 bernie
65 *#* Revision 1.13 2004/09/06 21:40:50 bernie
66 *#* Move buffer handling in chip-specific driver.
68 *#* Revision 1.12 2004/08/29 22:06:10 bernie
69 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
71 *#* Revision 1.10 2004/08/10 06:30:41 bernie
72 *#* Major redesign of serial bus policy handling.
74 *#* Revision 1.9 2004/08/02 20:20:29 aleph
75 *#* Merge from project_ks
77 *#* Revision 1.8 2004/07/29 22:57:09 bernie
78 *#* Several tweaks to reduce code size on ATmega8.
80 *#* Revision 1.7 2004/07/18 21:54:23 bernie
81 *#* Add ATmega8 support.
83 *#* Revision 1.5 2004/06/27 15:25:40 aleph
84 *#* Add missing callbacks for SPI;
85 *#* Change UNUSED() macro to new version with two args;
86 *#* Use TX line filling only on the correct KBUS serial port;
87 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
89 *#* Revision 1.4 2004/06/03 11:27:09 bernie
90 *#* Add dual-license information.
92 *#* Revision 1.3 2004/06/02 21:35:24 aleph
93 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
95 *#* Revision 1.2 2004/05/23 18:21:53 bernie
96 *#* Trim CVS logs and cleanup header info.
103 #include "hw.h" /* Required for bus macros overrides */
106 #include <drv/timer.h>
107 #include <mware/fifobuf.h>
109 #include <avr/signal.h>
114 * \name Hardware handshake (RTS/CTS).
118 #define RTS_ON do {} while (0)
121 #define RTS_OFF do {} while (0)
124 #define IS_CTS_ON true
127 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
133 * \name Overridable serial bus hooks
135 * These can be redefined in hw.h to implement
136 * special bus policies such as half-duplex, 485, etc.
140 * TXBEGIN TXCHAR TXEND TXOFF
141 * | __________|__________ | |
144 * ______ __ __ __ __ __ __ ________________
145 * \/ \/ \/ \/ \/ \/ \/
146 * ______/\__/\__/\__/\__/\__/\__/
152 #ifndef SER_UART0_BUS_TXINIT
154 * Default TXINIT macro - invoked in uart0_init()
156 * - Enable both the receiver and the transmitter
157 * - Enable only the RX complete interrupt
159 #define SER_UART0_BUS_TXINIT do { \
160 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
164 #ifndef SER_UART0_BUS_TXBEGIN
166 * Invoked before starting a transmission
168 * - Enable both the receiver and the transmitter
169 * - Enable both the RX complete and UDR empty interrupts
171 #define SER_UART0_BUS_TXBEGIN do { \
172 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
176 #ifndef SER_UART0_BUS_TXCHAR
178 * Invoked to send one character.
180 #define SER_UART0_BUS_TXCHAR(c) do { \
185 #ifndef SER_UART0_BUS_TXEND
187 * Invoked as soon as the txfifo becomes empty
189 * - Keep both the receiver and the transmitter enabled
190 * - Keep the RX complete interrupt enabled
191 * - Disable the UDR empty interrupt
193 #define SER_UART0_BUS_TXEND do { \
194 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
198 #ifndef SER_UART0_BUS_TXOFF
200 * \def SER_UART0_BUS_TXOFF
202 * Invoked after the last character has been transmitted
204 * The default is no action.
207 #define SER_UART0_BUS_TXOFF
211 #ifndef SER_UART1_BUS_TXINIT
212 /*! \sa SER_UART0_BUS_TXINIT */
213 #define SER_UART1_BUS_TXINIT do { \
214 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
217 #ifndef SER_UART1_BUS_TXBEGIN
218 /*! \sa SER_UART0_BUS_TXBEGIN */
219 #define SER_UART1_BUS_TXBEGIN do { \
220 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
223 #ifndef SER_UART1_BUS_TXCHAR
224 /*! \sa SER_UART0_BUS_TXCHAR */
225 #define SER_UART1_BUS_TXCHAR(c) do { \
229 #ifndef SER_UART1_BUS_TXEND
230 /*! \sa SER_UART0_BUS_TXEND */
231 #define SER_UART1_BUS_TXEND do { \
232 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
235 #ifndef SER_UART1_BUS_TXOFF
237 * \def SER_UART1_BUS_TXOFF
239 * \see SER_UART0_BUS_TXOFF
242 #define SER_UART1_BUS_TXOFF
248 /* SPI port and pin configuration */
249 #define SPI_PORT PORTB
251 #define SPI_SCK_BIT PB1
252 #define SPI_MOSI_BIT PB2
253 #define SPI_MISO_BIT PB3
255 /* USART register definitions */
256 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
257 #define AVR_HAS_UART1 1
258 #elif CPU_AVR_ATMEGA8
259 #define AVR_HAS_UART1 0
266 #define SIG_UART0_DATA SIG_UART_DATA
267 #define SIG_UART0_RECV SIG_UART_RECV
268 #elif CPU_AVR_ATMEGA103
269 #define AVR_HAS_UART1 0
274 #define SIG_UART0_DATA SIG_UART_DATA
275 #define SIG_UART0_RECV SIG_UART_RECV
277 #error Unknown architecture
282 * \def CONFIG_SER_STROBE
284 * This is a debug facility that can be used to
285 * monitor SER interrupt activity on an external pin.
287 * To use strobes, redefine the macros SER_STROBE_ON,
288 * SER_STROBE_OFF and SER_STROBE_INIT and set
289 * CONFIG_SER_STROBE to 1.
291 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
292 #define SER_STROBE_ON do {/*nop*/} while(0)
293 #define SER_STROBE_OFF do {/*nop*/} while(0)
294 #define SER_STROBE_INIT do {/*nop*/} while(0)
298 /* From the high-level serial driver */
299 extern struct Serial ser_handles[SER_CNT];
301 /* TX and RX buffers */
302 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
303 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
305 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
306 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
308 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
309 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
313 * Internal hardware state structure
315 * The \a sending variable is true while the transmission
316 * interrupt is retriggering itself.
318 * For the USARTs the \a sending flag is useful for taking specific
319 * actions before sending a burst of data, at the start of a trasmission
320 * but not before every char sent.
322 * For the SPI, this flag is necessary because the SPI sends and receives
323 * bytes at the same time and the SPI IRQ is unique for send/receive.
324 * The only way to start transmission is to write data in SPDR (this
325 * is done by spi_starttx()). We do this *only* if a transfer is
326 * not already started.
330 struct SerialHardware hw;
331 volatile bool sending;
336 * These are to trick GCC into *not* using absolute addressing mode
337 * when accessing ser_handles, which is very expensive.
339 * Accessing through these pointers generates much shorter
340 * (and hopefully faster) code.
342 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
344 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
346 struct Serial *ser_spi = &ser_handles[SER_SPI];
353 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
355 SER_UART0_BUS_TXINIT;
359 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
364 static void uart0_enabletxirq(struct SerialHardware *_hw)
366 struct AvrSerial *hw = (struct AvrSerial *)_hw;
369 * WARNING: racy code here! The tx interrupt sets hw->sending to false
370 * when it runs with an empty fifo. The order of statements in the
376 SER_UART0_BUS_TXBEGIN;
380 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
382 /* Compute baud-rate period */
383 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
385 #ifndef __AVR_ATmega103__
386 UBRR0H = (period) >> 8;
390 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
393 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
395 #if !CPU_AVR_ATMEGA103
396 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
402 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
404 SER_UART1_BUS_TXINIT;
409 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
414 static void uart1_enabletxirq(struct SerialHardware *_hw)
416 struct AvrSerial *hw = (struct AvrSerial *)_hw;
419 * WARNING: racy code here! The tx interrupt
420 * sets hw->sending to false when it runs with
421 * an empty fifo. The order of the statements
422 * in the if-block matters.
427 SER_UART1_BUS_TXBEGIN;
431 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
433 /* Compute baud-rate period */
434 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
436 UBRR1H = (period) >> 8;
439 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
442 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
444 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
447 #endif // AVR_HAS_UART1
449 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
452 * Set MOSI and SCK ports out, MISO in.
454 * The ATmega64/128 datasheet explicitly states that the input/output
455 * state of the SPI pins is not significant, as when the SPI is
456 * active the I/O port are overrided.
457 * This is *blatantly FALSE*.
459 * Moreover, the MISO pin on the board_kc *must* be in high impedance
460 * state even when the SPI is off, because the line is wired together
461 * with the KBus serial RX, and the transmitter of the slave boards
462 * would be unable to drive the line.
464 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
465 SPI_DDR &= ~BV(SPI_MISO_BIT);
466 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
467 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
470 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
473 /* Set all pins as inputs */
474 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
477 static void spi_starttx(struct SerialHardware *_hw)
479 struct AvrSerial *hw = (struct AvrSerial *)_hw;
482 IRQ_SAVE_DISABLE(flags);
484 /* Send data only if the SPI is not already transmitting */
485 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
488 SPDR = fifo_pop(&ser_spi->txfifo);
494 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
499 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
505 // FIXME: move into compiler.h? Ditch?
507 #define C99INIT(name,val) .name = val
508 #elif defined(__GNUC__)
509 #define C99INIT(name,val) name: val
511 #warning No designated initializers, double check your code
512 #define C99INIT(name,val) (val)
516 * High-level interface data structures
518 static const struct SerialHardwareVT UART0_VT =
520 C99INIT(init, uart0_init),
521 C99INIT(cleanup, uart0_cleanup),
522 C99INIT(setbaudrate, uart0_setbaudrate),
523 C99INIT(setparity, uart0_setparity),
524 C99INIT(enabletxirq, uart0_enabletxirq),
528 static const struct SerialHardwareVT UART1_VT =
530 C99INIT(init, uart1_init),
531 C99INIT(cleanup, uart1_cleanup),
532 C99INIT(setbaudrate, uart1_setbaudrate),
533 C99INIT(setparity, uart1_setparity),
534 C99INIT(enabletxirq, uart1_enabletxirq),
536 #endif // AVR_HAS_UART1
538 static const struct SerialHardwareVT SPI_VT =
540 C99INIT(init, spi_init),
541 C99INIT(cleanup, spi_cleanup),
542 C99INIT(setbaudrate, spi_setbaudrate),
543 C99INIT(setparity, spi_setparity),
544 C99INIT(enabletxirq, spi_starttx),
547 static struct AvrSerial UARTDescs[SER_CNT] =
551 C99INIT(table, &UART0_VT),
552 C99INIT(txbuffer, uart0_txbuffer),
553 C99INIT(rxbuffer, uart0_rxbuffer),
554 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
555 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
557 C99INIT(sending, false),
562 C99INIT(table, &UART1_VT),
563 C99INIT(txbuffer, uart1_txbuffer),
564 C99INIT(rxbuffer, uart1_rxbuffer),
565 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
566 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
568 C99INIT(sending, false),
573 C99INIT(table, &SPI_VT),
574 C99INIT(txbuffer, spi_txbuffer),
575 C99INIT(rxbuffer, spi_rxbuffer),
576 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
577 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
579 C99INIT(sending, false),
583 struct SerialHardware* ser_hw_getdesc(int unit)
585 ASSERT(unit < SER_CNT);
586 return &UARTDescs[unit].hw;
594 #if CONFIG_SER_HWHANDSHAKE
596 //! This interrupt is triggered when the CTS line goes high
599 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
600 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
601 cbi(EIMSK, EIMSKB_CTS);
604 #endif // CONFIG_SER_HWHANDSHAKE
608 * Serial 0 TX interrupt handler
610 SIGNAL(SIG_UART0_DATA)
614 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
616 if (fifo_isempty(txfifo))
619 #ifndef SER_UART0_BUS_TXOFF
620 UARTDescs[SER_UART0].sending = false;
623 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
626 // Disable rx interrupt and tx, enable CTS interrupt
628 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
629 sbi(EIFR, EIMSKB_CTS);
630 sbi(EIMSK, EIMSKB_CTS);
635 char c = fifo_pop(txfifo);
636 SER_UART0_BUS_TXCHAR(c);
642 #ifdef SER_UART0_BUS_TXOFF
644 * Serial port 0 TX complete interrupt handler.
646 * This IRQ is usually disabled. The UDR-empty interrupt
647 * enables it when there's no more data to transmit.
648 * We need to wait until the last character has been
649 * transmitted before switching the 485 transceiver to
652 * The txfifo might have been refilled by putchar() while
653 * we were waiting for the transmission complete interrupt.
654 * In this case, we must restart the UDR empty interrupt,
655 * otherwise we'd stop the serial port with some data
656 * still pending in the buffer.
658 SIGNAL(SIG_UART0_TRANS)
662 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
663 if (fifo_isempty(txfifo))
666 UARTDescs[SER_UART0].sending = false;
669 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
673 #endif /* SER_UART0_BUS_TXOFF */
679 * Serial 1 TX interrupt handler
681 SIGNAL(SIG_UART1_DATA)
685 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
687 if (fifo_isempty(txfifo))
690 #ifndef SER_UART1_BUS_TXOFF
691 UARTDescs[SER_UART1].sending = false;
694 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
697 // Disable rx interrupt and tx, enable CTS interrupt
699 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
700 sbi(EIFR, EIMSKB_CTS);
701 sbi(EIMSK, EIMSKB_CTS);
706 char c = fifo_pop(txfifo);
707 SER_UART1_BUS_TXCHAR(c);
713 #ifdef SER_UART1_BUS_TXOFF
715 * Serial port 1 TX complete interrupt handler.
717 * \sa port 0 TX complete handler.
719 SIGNAL(SIG_UART1_TRANS)
723 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
724 if (fifo_isempty(txfifo))
727 UARTDescs[SER_UART1].sending = false;
730 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
734 #endif /* SER_UART1_BUS_TXOFF */
736 #endif // AVR_HAS_UART1
740 * Serial 0 RX complete interrupt handler.
742 * This handler is interruptible.
743 * Interrupt are reenabled as soon as recv complete interrupt is
744 * disabled. Using INTERRUPT() is troublesome when the serial
745 * is heavily loaded, because an interrupt could be retriggered
746 * when executing the handler prologue before RXCIE is disabled.
748 * \note The code that re-enables interrupts is commented out
749 * because in some nasty cases the interrupt is retriggered.
750 * This is probably due to the RXC flag being set before
751 * RXCIE is cleared. Unfortunately the RXC flag is read-only
752 * and can't be cleared by code.
754 SIGNAL(SIG_UART0_RECV)
758 /* Disable Recv complete IRQ */
759 //UCSR0B &= ~BV(RXCIE);
762 /* Should be read before UDR */
763 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
765 /* To clear the RXC flag we must _always_ read the UDR even when we're
766 * not going to accept the incoming data, otherwise a new interrupt
767 * will occur once the handler terminates.
770 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
772 if (fifo_isfull(rxfifo))
773 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
776 fifo_push(rxfifo, c);
777 #if CONFIG_SER_HWHANDSHAKE
778 if (fifo_isfull(rxfifo))
783 /* Reenable receive complete int */
785 //UCSR0B |= BV(RXCIE);
794 * Serial 1 RX complete interrupt handler.
796 * This handler is interruptible.
797 * Interrupt are reenabled as soon as recv complete interrupt is
798 * disabled. Using INTERRUPT() is troublesome when the serial
799 * is heavily loaded, because an interrupt could be retriggered
800 * when executing the handler prologue before RXCIE is disabled.
802 * \see SIGNAL(SIG_UART0_RECV)
804 SIGNAL(SIG_UART1_RECV)
808 /* Disable Recv complete IRQ */
809 //UCSR1B &= ~BV(RXCIE);
812 /* Should be read before UDR */
813 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
815 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
816 * not going to accept the incoming data
819 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
820 //ASSERT_VALID_FIFO(rxfifo);
822 if (UNLIKELY(fifo_isfull(rxfifo)))
823 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
826 fifo_push(rxfifo, c);
827 #if CONFIG_SER_HWHANDSHAKE
828 if (fifo_isfull(rxfifo))
832 /* Re-enable receive complete int */
834 //UCSR1B |= BV(RXCIE);
839 #endif // AVR_HAS_UART1
843 * SPI interrupt handler
847 /* Read incoming byte. */
848 if (!fifo_isfull(&ser_spi->rxfifo))
849 fifo_push(&ser_spi->rxfifo, SPDR);
853 ser_spi->status |= SERRF_RXFIFOOVERRUN;
857 if (!fifo_isempty(&ser_spi->txfifo))
858 SPDR = fifo_pop(&ser_spi->txfifo);
860 UARTDescs[SER_SPI].sending = false;