4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.13 2004/09/06 21:40:50 bernie
42 *#* Move buffer handling in chip-specific driver.
44 *#* Revision 1.12 2004/08/29 22:06:10 bernie
45 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
47 *#* Revision 1.10 2004/08/10 06:30:41 bernie
48 *#* Major redesign of serial bus policy handling.
50 *#* Revision 1.9 2004/08/02 20:20:29 aleph
51 *#* Merge from project_ks
53 *#* Revision 1.8 2004/07/29 22:57:09 bernie
54 *#* Several tweaks to reduce code size on ATmega8.
56 *#* Revision 1.7 2004/07/18 21:54:23 bernie
57 *#* Add ATmega8 support.
59 *#* Revision 1.5 2004/06/27 15:25:40 aleph
60 *#* Add missing callbacks for SPI;
61 *#* Change UNUSED() macro to new version with two args;
62 *#* Use TX line filling only on the correct KBUS serial port;
63 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
65 *#* Revision 1.4 2004/06/03 11:27:09 bernie
66 *#* Add dual-license information.
68 *#* Revision 1.3 2004/06/02 21:35:24 aleph
69 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
71 *#* Revision 1.2 2004/05/23 18:21:53 bernie
72 *#* Trim CVS logs and cleanup header info.
79 #include "hw.h" /* Required for bus macros overrides */
81 #include <drv/kdebug.h>
82 #include <drv/timer.h>
83 #include <mware/fifobuf.h>
85 #include <avr/signal.h>
89 * \name Hardware handshake (RTS/CTS).
93 #define RTS_ON do {} while (0)
96 #define RTS_OFF do {} while (0)
99 #define IS_CTS_ON true
102 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
108 * \name Overridable serial bus hooks
110 * These can be redefined in hw.h to implement
111 * special bus policies such as half-duplex, 485, etc.
115 * TXBEGIN TXCHAR TXEND TXOFF
116 * | __________|__________ | |
119 * ______ __ __ __ __ __ __ ________________
120 * \/ \/ \/ \/ \/ \/ \/
121 * ______/\__/\__/\__/\__/\__/\__/
127 #ifndef SER_UART0_BUS_TXINIT
129 * Default TXINIT macro - invoked in uart0_init()
131 * - Enable both the receiver and the transmitter
132 * - Enable only the RX complete interrupt
134 #define SER_UART0_BUS_TXINIT do { \
135 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
139 #ifndef SER_UART0_BUS_TXBEGIN
141 * Invoked before starting a transmission
143 * - Enable both the receiver and the transmitter
144 * - Enable both the RX complete and UDR empty interrupts
146 #define SER_UART0_BUS_TXBEGIN do { \
147 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
151 #ifndef SER_UART0_BUS_TXCHAR
153 * Invoked to send one character.
155 #define SER_UART0_BUS_TXCHAR(c) do { \
160 #ifndef SER_UART0_BUS_TXEND
162 * Invoked as soon as the txfifo becomes empty
164 * - Keep both the receiver and the transmitter enabled
165 * - Keep the RX complete interrupt enabled
166 * - Disable the UDR empty interrupt
168 #define SER_UART0_BUS_TXEND do { \
169 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
173 #ifndef SER_UART0_BUS_TXOFF
175 * \def SER_UART0_BUS_TXOFF
177 * Invoked after the last character has been transmitted
179 * The default is no action.
183 #ifndef SER_UART1_BUS_TXINIT
184 /*! \sa SER_UART0_BUS_TXINIT */
185 #define SER_UART1_BUS_TXINIT do { \
186 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
189 #ifndef SER_UART1_BUS_TXBEGIN
190 /*! \sa SER_UART0_BUS_TXBEGIN */
191 #define SER_UART1_BUS_TXBEGIN do { \
192 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
195 #ifndef SER_UART1_BUS_TXCHAR
196 /*! \sa SER_UART0_BUS_TXCHAR */
197 #define SER_UART1_BUS_TXCHAR(c) do { \
201 #ifndef SER_UART1_BUS_TXEND
202 /*! \sa SER_UART0_BUS_TXEND */
203 #define SER_UART1_BUS_TXEND do { \
204 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
207 #ifndef SER_UART1_BUS_TXOFF
209 * \def SER_UART1_BUS_TXOFF
211 * \see SER_UART0_BUS_TXOFF
217 /* SPI port and pin configuration */
218 #define SPI_PORT PORTB
220 #define SPI_SCK_BIT PORTB1
221 #define SPI_MOSI_BIT PORTB2
222 #define SPI_MISO_BIT PORTB3
224 /* USART registers definitions */
225 #if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
226 #define AVR_HAS_UART1 1
227 #elif defined(__AVR_ATmega8__)
228 #define AVR_HAS_UART1 0
235 #define SIG_UART0_DATA SIG_UART_DATA
236 #define SIG_UART0_RECV SIG_UART_RECV
237 #elif defined(__AVR_ATmega103__)
238 #define AVR_HAS_UART1 0
243 #define SIG_UART0_DATA SIG_UART_DATA
244 #define SIG_UART0_RECV SIG_UART_RECV
246 #error Unknown architecture
251 * \def CONFIG_SER_STROBE
253 * This is a debug facility that can be used to
254 * monitor SER interrupt activity on an external pin.
256 * To use strobes, redefine the macros SER_STROBE_ON,
257 * SER_STROBE_OFF and SER_STROBE_INIT and set
258 * CONFIG_SER_STROBE to 1.
260 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
261 #define SER_STROBE_ON do {/*nop*/} while(0)
262 #define SER_STROBE_OFF do {/*nop*/} while(0)
263 #define SER_STROBE_INIT do {/*nop*/} while(0)
267 /* From the high-level serial driver */
268 extern struct Serial ser_handles[SER_CNT];
270 /* TX and RX buffers */
271 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
272 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
274 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
275 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
277 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
278 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
282 * Internal hardware state structure
284 * The \a sending variable is true while the transmission
285 * interrupt is retriggering itself.
287 * For the USARTs the \a sending flag is useful for taking specific
288 * actions before sending a burst of data, at the start of a trasmission
289 * but not before every char sent.
291 * For the SPI, this flag is necessary because the SPI sends and receives
292 * bytes at the same time and the SPI IRQ is unique for send/receive.
293 * The only way to start transmission is to write data in SPDR (this
294 * is done by spi_starttx()). We do this *only* if a transfer is
295 * not already started.
299 struct SerialHardware hw;
300 volatile bool sending;
305 * These are to trick GCC into *not* using
306 * absolute addressing mode when accessing
307 * ser_handles, which is very expensive.
309 * Accessing through these pointers generates
310 * much shorter (and hopefully faster) code.
312 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
314 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
316 struct Serial *ser_spi = &ser_handles[SER_SPI];
323 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
325 SER_UART0_BUS_TXINIT;
329 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
334 static void uart0_enabletxirq(struct SerialHardware *_hw)
336 struct AvrSerial *hw = (struct AvrSerial *)_hw;
339 * WARNING: racy code here! The tx interrupt
340 * sets hw->sending to false when it runs with
341 * an empty fifo. The order of the statements
342 * in the if-block matters.
347 SER_UART0_BUS_TXBEGIN;
351 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
353 /* Compute baud-rate period */
354 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
356 #ifndef __AVR_ATmega103__
357 UBRR0H = (period) >> 8;
361 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
364 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
366 #ifndef __AVR_ATmega103__
367 UCSR0C |= (parity) << UPM0;
373 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
375 SER_UART1_BUS_TXINIT;
380 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
385 static void uart1_enabletxirq(struct SerialHardware *_hw)
387 struct AvrSerial *hw = (struct AvrSerial *)_hw;
390 * WARNING: racy code here! The tx interrupt
391 * sets hw->sending to false when it runs with
392 * an empty fifo. The order of the statements
393 * in the if-block matters.
398 SER_UART1_BUS_TXBEGIN;
402 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
404 /* Compute baud-rate period */
405 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
407 UBRR1H = (period) >> 8;
410 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
413 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
415 UCSR1C |= (parity) << UPM0;
418 #endif // AVR_HAS_UART1
420 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
423 * Set MOSI and SCK ports out, MISO in.
425 * The ATmega64/128 datasheet explicitly states that the input/output
426 * state of the SPI pins is not significant, as when the SPI is
427 * active the I/O port are overrided.
428 * This is *blatantly FALSE*.
430 * Moreover, the MISO pin on the board_kc *must* be in high impedance
431 * state even when the SPI is off, because the line is wired together
432 * with the KBus serial RX, and the transmitter of the slave boards
433 * would be unable to drive the line.
435 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
436 SPI_DDR &= ~BV(SPI_MISO_BIT);
437 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
438 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
441 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
444 /* Set all pins as inputs */
445 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
448 static void spi_starttx(struct SerialHardware *_hw)
450 struct AvrSerial *hw = (struct AvrSerial *)_hw;
453 DISABLE_IRQSAVE(flags);
455 /* Send data only if the SPI is not already transmitting */
456 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
459 SPDR = fifo_pop(&ser_spi->txfifo);
462 ENABLE_IRQRESTORE(flags);
465 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
470 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
478 * High-level interface data structures
480 static const struct SerialHardwareVT UART0_VT =
483 .cleanup = uart0_cleanup,
484 .setbaudrate = uart0_setbaudrate,
485 .setparity = uart0_setparity,
486 .enabletxirq = uart0_enabletxirq,
490 static const struct SerialHardwareVT UART1_VT =
493 .cleanup = uart1_cleanup,
494 .setbaudrate = uart1_setbaudrate,
495 .setparity = uart1_setparity,
496 .enabletxirq = uart1_enabletxirq,
498 #endif // AVR_HAS_UART1
500 static const struct SerialHardwareVT SPI_VT =
503 .cleanup = spi_cleanup,
504 .setbaudrate = spi_setbaudrate,
505 .setparity = spi_setparity,
506 .enabletxirq = spi_starttx,
509 static struct AvrSerial UARTDescs[SER_CNT] =
514 .txbuffer = uart0_txbuffer,
515 .rxbuffer = uart0_rxbuffer,
516 .txbuffer_size = CONFIG_UART0_TXBUFSIZE,
517 .rxbuffer_size = CONFIG_UART0_RXBUFSIZE,
525 .txbuffer = uart1_txbuffer,
526 .rxbuffer = uart1_rxbuffer,
527 .txbuffer_size = CONFIG_UART1_TXBUFSIZE,
528 .rxbuffer_size = CONFIG_UART1_RXBUFSIZE,
536 .txbuffer = spi_txbuffer,
537 .rxbuffer = spi_rxbuffer,
538 .txbuffer_size = CONFIG_SPI_TXBUFSIZE,
539 .rxbuffer_size = CONFIG_SPI_RXBUFSIZE,
545 struct SerialHardware* ser_hw_getdesc(int unit)
547 ASSERT(unit < SER_CNT);
548 return &UARTDescs[unit].hw;
557 #if CONFIG_SER_HWHANDSHAKE
559 //! This interrupt is triggered when the CTS line goes high
562 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
563 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
564 cbi(EIMSK, EIMSKB_CTS);
567 #endif // CONFIG_SER_HWHANDSHAKE
571 * Serial 0 TX interrupt handler
573 SIGNAL(SIG_UART0_DATA)
577 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
579 if (fifo_isempty(txfifo))
582 #ifndef SER_UART0_BUS_TXOFF
583 UARTDescs[SER_UART0].sending = false;
586 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
589 // Disable rx interrupt and tx, enable CTS interrupt
591 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
592 sbi(EIFR, EIMSKB_CTS);
593 sbi(EIMSK, EIMSKB_CTS);
598 char c = fifo_pop(txfifo);
599 SER_UART0_BUS_TXCHAR(c);
605 #ifdef SER_UART0_BUS_TXOFF
607 * Serial port 0 TX complete interrupt handler.
609 * This IRQ is usually disabled. The UDR-empty interrupt
610 * enables it when there's no more data to transmit.
611 * We need to wait until the last character has been
612 * transmitted before switching the 485 transceiver to
615 * The txfifo might have been refilled by putchar() while
616 * we were waiting for the transmission complete interrupt.
617 * In this case, we must restart the UDR empty interrupt,
618 * otherwise we'd stop the serial port with some data
619 * still pending in the buffer.
621 SIGNAL(SIG_UART0_TRANS)
625 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
626 if (fifo_isempty(txfifo))
629 UARTDescs[SER_UART0].sending = false;
632 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
636 #endif /* SER_UART0_BUS_TXOFF */
642 * Serial 1 TX interrupt handler
644 SIGNAL(SIG_UART1_DATA)
648 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
650 if (fifo_isempty(txfifo))
653 #ifndef SER_UART1_BUS_TXOFF
654 UARTDescs[SER_UART1].sending = false;
657 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
660 // Disable rx interrupt and tx, enable CTS interrupt
662 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
663 sbi(EIFR, EIMSKB_CTS);
664 sbi(EIMSK, EIMSKB_CTS);
669 char c = fifo_pop(txfifo);
670 SER_UART1_BUS_TXCHAR(c);
676 #ifdef SER_UART1_BUS_TXOFF
678 * Serial port 1 TX complete interrupt handler.
680 * \sa port 0 TX complete handler.
682 SIGNAL(SIG_UART1_TRANS)
686 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
687 if (fifo_isempty(txfifo))
690 UARTDescs[SER_UART1].sending = false;
693 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
697 #endif /* SER_UART1_BUS_TXOFF */
699 #endif // AVR_HAS_UART1
703 * Serial 0 RX complete interrupt handler.
705 * This handler is interruptible.
706 * Interrupt are reenabled as soon as recv complete interrupt is
707 * disabled. Using INTERRUPT() is troublesome when the serial
708 * is heavily loaded, because an interrupt could be retriggered
709 * when executing the handler prologue before RXCIE is disabled.
711 * \note The code that re-enables interrupts is commented out
712 * because in some nasty cases the interrupt is retriggered.
713 * This is probably due to the RXC flag being set before
714 * RXCIE is cleared. Unfortunately the RXC flag is read-only
715 * and can't be cleared by code.
717 SIGNAL(SIG_UART0_RECV)
721 /* Disable Recv complete IRQ */
722 //UCSR0B &= ~BV(RXCIE);
725 /* Should be read before UDR */
726 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
728 /* To clear the RXC flag we must _always_ read the UDR even when we're
729 * not going to accept the incoming data, otherwise a new interrupt
730 * will occur once the handler terminates.
733 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
735 if (fifo_isfull(rxfifo))
736 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
739 fifo_push(rxfifo, c);
740 #if CONFIG_SER_HWHANDSHAKE
741 if (fifo_isfull(rxfifo))
746 /* Reenable receive complete int */
748 //UCSR0B |= BV(RXCIE);
757 * Serial 1 RX complete interrupt handler.
759 * This handler is interruptible.
760 * Interrupt are reenabled as soon as recv complete interrupt is
761 * disabled. Using INTERRUPT() is troublesome when the serial
762 * is heavily loaded, because an interrupt could be retriggered
763 * when executing the handler prologue before RXCIE is disabled.
765 * \see SIGNAL(SIG_UART0_RECV)
767 SIGNAL(SIG_UART1_RECV)
771 /* Disable Recv complete IRQ */
772 //UCSR1B &= ~BV(RXCIE);
775 /* Should be read before UDR */
776 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
778 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
779 * not going to accept the incoming data
782 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
783 //ASSERT_VALID_FIFO(rxfifo);
785 if (UNLIKELY(fifo_isfull(rxfifo)))
786 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
789 fifo_push(rxfifo, c);
790 #if CONFIG_SER_HWHANDSHAKE
791 if (fifo_isfull(rxfifo))
795 /* Reenable receive complete int */
796 //UCSR1B |= BV(RXCIE);
801 #endif // AVR_HAS_UART1
805 * SPI interrupt handler
809 /* Read incoming byte. */
810 if (!fifo_isfull(&ser_spi->rxfifo))
811 fifo_push(&ser_spi->rxfifo, SPDR);
815 ser_spi->status |= SERRF_RXFIFOOVERRUN;
819 if (!fifo_isempty(&ser_spi->txfifo))
820 SPDR = fifo_pop(&ser_spi->txfifo);
822 UARTDescs[SER_SPI].sending = false;