4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
6 * This file is part of DevLib - See devlib/README for information.
9 * \brief AVR UART and SPI I/O driver
11 * Rationale for project_ks hardware.
13 * The serial 0 on the board_kf board is used to communicate with the
14 * smart card, which has the TX and RX lines connected together. To
15 * allow the smart card to drive the RX line of the CPU the CPU TX has
16 * to be in a high impedance state.
17 * Whenever a transmission is done and there is nothing more to send
18 * the transmitter is turn off. The output pin is held in input with
19 * pull-up enabled, to avoid capturing noise from the nearby RX line.
21 * The line on the KBus port must keep sending data, even when
22 * there is nothing to transmit, because a burst data transfer
23 * generates noise on the audio channels.
24 * This is accomplished using the multiprocessor mode of the
25 * ATmega64/128 serial.
27 * The receiver keeps the MPCM bit always on. When useful data
28 * is trasmitted the address bit is set. The receiver hardware
29 * consider the frame as address info and receive it.
30 * When useless fill bytes are sent the address bit is cleared
31 * and the receiver will ignore them, avoiding useless triggering
35 * \author Bernardo Innocenti <bernie@develer.com>
36 * \author Stefano Fedrigo <aleph@develer.com>
41 *#* Revision 1.20 2004/12/13 11:51:43 bernie
42 *#* Fix a latent bug with reentrant serial IRQs.
44 *#* Revision 1.19 2004/12/13 11:51:08 bernie
45 *#* DISABLE_INTS/ENABLE_INTS: Convert to IRQ_DISABLE/IRQ_ENABLE.
47 *#* Revision 1.18 2004/12/08 08:03:48 bernie
50 *#* Revision 1.17 2004/10/19 07:52:35 bernie
51 *#* Reset parity bits before overwriting them (Fixed by batt in project_ks).
53 *#* Revision 1.16 2004/10/03 18:45:48 bernie
54 *#* Convert to new-style config macros; Allow compiling with a C++ compiler (mostly).
56 *#* Revision 1.15 2004/09/14 21:05:36 bernie
57 *#* Use debug.h instead of kdebug.h; Use new AVR pin names; Spelling fixes.
59 *#* Revision 1.14 2004/09/06 21:50:00 bernie
62 *#* Revision 1.13 2004/09/06 21:40:50 bernie
63 *#* Move buffer handling in chip-specific driver.
65 *#* Revision 1.12 2004/08/29 22:06:10 bernie
66 *#* Fix a bug in the (unused) RTS/CTS code; Clarify documentation.
68 *#* Revision 1.10 2004/08/10 06:30:41 bernie
69 *#* Major redesign of serial bus policy handling.
71 *#* Revision 1.9 2004/08/02 20:20:29 aleph
72 *#* Merge from project_ks
74 *#* Revision 1.8 2004/07/29 22:57:09 bernie
75 *#* Several tweaks to reduce code size on ATmega8.
77 *#* Revision 1.7 2004/07/18 21:54:23 bernie
78 *#* Add ATmega8 support.
80 *#* Revision 1.5 2004/06/27 15:25:40 aleph
81 *#* Add missing callbacks for SPI;
82 *#* Change UNUSED() macro to new version with two args;
83 *#* Use TX line filling only on the correct KBUS serial port;
84 *#* Fix nasty IRQ disabling bug in recv complete hander for port 1.
86 *#* Revision 1.4 2004/06/03 11:27:09 bernie
87 *#* Add dual-license information.
89 *#* Revision 1.3 2004/06/02 21:35:24 aleph
90 *#* Serial enhancements: interruptible receive handler and 8 bit serial status for AVR; remove volatile attribute to FIFOBuffer, useless for new fifobuf routens
92 *#* Revision 1.2 2004/05/23 18:21:53 bernie
93 *#* Trim CVS logs and cleanup header info.
100 #include "hw.h" /* Required for bus macros overrides */
103 #include <drv/timer.h>
104 #include <mware/fifobuf.h>
106 #include <avr/signal.h>
111 * \name Hardware handshake (RTS/CTS).
115 #define RTS_ON do {} while (0)
118 #define RTS_OFF do {} while (0)
121 #define IS_CTS_ON true
124 #define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
130 * \name Overridable serial bus hooks
132 * These can be redefined in hw.h to implement
133 * special bus policies such as half-duplex, 485, etc.
137 * TXBEGIN TXCHAR TXEND TXOFF
138 * | __________|__________ | |
141 * ______ __ __ __ __ __ __ ________________
142 * \/ \/ \/ \/ \/ \/ \/
143 * ______/\__/\__/\__/\__/\__/\__/
149 #ifndef SER_UART0_BUS_TXINIT
151 * Default TXINIT macro - invoked in uart0_init()
153 * - Enable both the receiver and the transmitter
154 * - Enable only the RX complete interrupt
156 #define SER_UART0_BUS_TXINIT do { \
157 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
161 #ifndef SER_UART0_BUS_TXBEGIN
163 * Invoked before starting a transmission
165 * - Enable both the receiver and the transmitter
166 * - Enable both the RX complete and UDR empty interrupts
168 #define SER_UART0_BUS_TXBEGIN do { \
169 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
173 #ifndef SER_UART0_BUS_TXCHAR
175 * Invoked to send one character.
177 #define SER_UART0_BUS_TXCHAR(c) do { \
182 #ifndef SER_UART0_BUS_TXEND
184 * Invoked as soon as the txfifo becomes empty
186 * - Keep both the receiver and the transmitter enabled
187 * - Keep the RX complete interrupt enabled
188 * - Disable the UDR empty interrupt
190 #define SER_UART0_BUS_TXEND do { \
191 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
195 #ifndef SER_UART0_BUS_TXOFF
197 * \def SER_UART0_BUS_TXOFF
199 * Invoked after the last character has been transmitted
201 * The default is no action.
204 #define SER_UART0_BUS_TXOFF
208 #ifndef SER_UART1_BUS_TXINIT
209 /*! \sa SER_UART0_BUS_TXINIT */
210 #define SER_UART1_BUS_TXINIT do { \
211 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
214 #ifndef SER_UART1_BUS_TXBEGIN
215 /*! \sa SER_UART0_BUS_TXBEGIN */
216 #define SER_UART1_BUS_TXBEGIN do { \
217 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
220 #ifndef SER_UART1_BUS_TXCHAR
221 /*! \sa SER_UART0_BUS_TXCHAR */
222 #define SER_UART1_BUS_TXCHAR(c) do { \
226 #ifndef SER_UART1_BUS_TXEND
227 /*! \sa SER_UART0_BUS_TXEND */
228 #define SER_UART1_BUS_TXEND do { \
229 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
232 #ifndef SER_UART1_BUS_TXOFF
234 * \def SER_UART1_BUS_TXOFF
236 * \see SER_UART0_BUS_TXOFF
239 #define SER_UART1_BUS_TXOFF
245 /* SPI port and pin configuration */
246 #define SPI_PORT PORTB
248 #define SPI_SCK_BIT PB1
249 #define SPI_MOSI_BIT PB2
250 #define SPI_MISO_BIT PB3
252 /* USART register definitions */
253 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
254 #define AVR_HAS_UART1 1
255 #elif CPU_AVR_ATMEGA8
256 #define AVR_HAS_UART1 0
263 #define SIG_UART0_DATA SIG_UART_DATA
264 #define SIG_UART0_RECV SIG_UART_RECV
265 #elif CPU_AVR_ATMEGA103
266 #define AVR_HAS_UART1 0
271 #define SIG_UART0_DATA SIG_UART_DATA
272 #define SIG_UART0_RECV SIG_UART_RECV
274 #error Unknown architecture
279 * \def CONFIG_SER_STROBE
281 * This is a debug facility that can be used to
282 * monitor SER interrupt activity on an external pin.
284 * To use strobes, redefine the macros SER_STROBE_ON,
285 * SER_STROBE_OFF and SER_STROBE_INIT and set
286 * CONFIG_SER_STROBE to 1.
288 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
289 #define SER_STROBE_ON do {/*nop*/} while(0)
290 #define SER_STROBE_OFF do {/*nop*/} while(0)
291 #define SER_STROBE_INIT do {/*nop*/} while(0)
295 /* From the high-level serial driver */
296 extern struct Serial ser_handles[SER_CNT];
298 /* TX and RX buffers */
299 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
300 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
302 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
303 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
305 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
306 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
310 * Internal hardware state structure
312 * The \a sending variable is true while the transmission
313 * interrupt is retriggering itself.
315 * For the USARTs the \a sending flag is useful for taking specific
316 * actions before sending a burst of data, at the start of a trasmission
317 * but not before every char sent.
319 * For the SPI, this flag is necessary because the SPI sends and receives
320 * bytes at the same time and the SPI IRQ is unique for send/receive.
321 * The only way to start transmission is to write data in SPDR (this
322 * is done by spi_starttx()). We do this *only* if a transfer is
323 * not already started.
327 struct SerialHardware hw;
328 volatile bool sending;
333 * These are to trick GCC into *not* using absolute addressing mode
334 * when accessing ser_handles, which is very expensive.
336 * Accessing through these pointers generates much shorter
337 * (and hopefully faster) code.
339 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
341 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
343 struct Serial *ser_spi = &ser_handles[SER_SPI];
350 static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
352 SER_UART0_BUS_TXINIT;
356 static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
361 static void uart0_enabletxirq(struct SerialHardware *_hw)
363 struct AvrSerial *hw = (struct AvrSerial *)_hw;
366 * WARNING: racy code here! The tx interrupt sets hw->sending to false
367 * when it runs with an empty fifo. The order of statements in the
373 SER_UART0_BUS_TXBEGIN;
377 static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
379 /* Compute baud-rate period */
380 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
382 #ifndef __AVR_ATmega103__
383 UBRR0H = (period) >> 8;
387 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
390 static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
392 #if !CPU_AVR_ATMEGA103
393 UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
399 static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
401 SER_UART1_BUS_TXINIT;
406 static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
411 static void uart1_enabletxirq(struct SerialHardware *_hw)
413 struct AvrSerial *hw = (struct AvrSerial *)_hw;
416 * WARNING: racy code here! The tx interrupt
417 * sets hw->sending to false when it runs with
418 * an empty fifo. The order of the statements
419 * in the if-block matters.
424 SER_UART1_BUS_TXBEGIN;
428 static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
430 /* Compute baud-rate period */
431 uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
433 UBRR1H = (period) >> 8;
436 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
439 static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
441 UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
444 #endif // AVR_HAS_UART1
446 static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
449 * Set MOSI and SCK ports out, MISO in.
451 * The ATmega64/128 datasheet explicitly states that the input/output
452 * state of the SPI pins is not significant, as when the SPI is
453 * active the I/O port are overrided.
454 * This is *blatantly FALSE*.
456 * Moreover, the MISO pin on the board_kc *must* be in high impedance
457 * state even when the SPI is off, because the line is wired together
458 * with the KBus serial RX, and the transmitter of the slave boards
459 * would be unable to drive the line.
461 SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
462 SPI_DDR &= ~BV(SPI_MISO_BIT);
463 /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
464 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
467 static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
470 /* Set all pins as inputs */
471 SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
474 static void spi_starttx(struct SerialHardware *_hw)
476 struct AvrSerial *hw = (struct AvrSerial *)_hw;
479 DISABLE_IRQSAVE(flags);
481 /* Send data only if the SPI is not already transmitting */
482 if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
485 SPDR = fifo_pop(&ser_spi->txfifo);
488 ENABLE_IRQRESTORE(flags);
491 static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
496 static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
502 // FIXME: move into compiler.h? Ditch?
504 #define C99INIT(name,val) .name = val
505 #elif defined(__GNUC__)
506 #define C99INIT(name,val) name: val
508 #warning No designated initializers, double check your code
509 #define C99INIT(name,val) (val)
513 * High-level interface data structures
515 static const struct SerialHardwareVT UART0_VT =
517 C99INIT(init, uart0_init),
518 C99INIT(cleanup, uart0_cleanup),
519 C99INIT(setbaudrate, uart0_setbaudrate),
520 C99INIT(setparity, uart0_setparity),
521 C99INIT(enabletxirq, uart0_enabletxirq),
525 static const struct SerialHardwareVT UART1_VT =
527 C99INIT(init, uart1_init),
528 C99INIT(cleanup, uart1_cleanup),
529 C99INIT(setbaudrate, uart1_setbaudrate),
530 C99INIT(setparity, uart1_setparity),
531 C99INIT(enabletxirq, uart1_enabletxirq),
533 #endif // AVR_HAS_UART1
535 static const struct SerialHardwareVT SPI_VT =
537 C99INIT(init, spi_init),
538 C99INIT(cleanup, spi_cleanup),
539 C99INIT(setbaudrate, spi_setbaudrate),
540 C99INIT(setparity, spi_setparity),
541 C99INIT(enabletxirq, spi_starttx),
544 static struct AvrSerial UARTDescs[SER_CNT] =
548 C99INIT(table, &UART0_VT),
549 C99INIT(txbuffer, uart0_txbuffer),
550 C99INIT(rxbuffer, uart0_rxbuffer),
551 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
552 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
554 C99INIT(sending, false),
559 C99INIT(table, &UART1_VT),
560 C99INIT(txbuffer, uart1_txbuffer),
561 C99INIT(rxbuffer, uart1_rxbuffer),
562 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
563 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
565 C99INIT(sending, false),
570 C99INIT(table, &SPI_VT),
571 C99INIT(txbuffer, spi_txbuffer),
572 C99INIT(rxbuffer, spi_rxbuffer),
573 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
574 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
576 C99INIT(sending, false),
580 struct SerialHardware* ser_hw_getdesc(int unit)
582 ASSERT(unit < SER_CNT);
583 return &UARTDescs[unit].hw;
591 #if CONFIG_SER_HWHANDSHAKE
593 //! This interrupt is triggered when the CTS line goes high
596 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
597 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
598 cbi(EIMSK, EIMSKB_CTS);
601 #endif // CONFIG_SER_HWHANDSHAKE
605 * Serial 0 TX interrupt handler
607 SIGNAL(SIG_UART0_DATA)
611 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
613 if (fifo_isempty(txfifo))
616 #ifndef SER_UART0_BUS_TXOFF
617 UARTDescs[SER_UART0].sending = false;
620 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
623 // Disable rx interrupt and tx, enable CTS interrupt
625 UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
626 sbi(EIFR, EIMSKB_CTS);
627 sbi(EIMSK, EIMSKB_CTS);
632 char c = fifo_pop(txfifo);
633 SER_UART0_BUS_TXCHAR(c);
639 #ifdef SER_UART0_BUS_TXOFF
641 * Serial port 0 TX complete interrupt handler.
643 * This IRQ is usually disabled. The UDR-empty interrupt
644 * enables it when there's no more data to transmit.
645 * We need to wait until the last character has been
646 * transmitted before switching the 485 transceiver to
649 * The txfifo might have been refilled by putchar() while
650 * we were waiting for the transmission complete interrupt.
651 * In this case, we must restart the UDR empty interrupt,
652 * otherwise we'd stop the serial port with some data
653 * still pending in the buffer.
655 SIGNAL(SIG_UART0_TRANS)
659 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
660 if (fifo_isempty(txfifo))
663 UARTDescs[SER_UART0].sending = false;
666 UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
670 #endif /* SER_UART0_BUS_TXOFF */
676 * Serial 1 TX interrupt handler
678 SIGNAL(SIG_UART1_DATA)
682 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
684 if (fifo_isempty(txfifo))
687 #ifndef SER_UART1_BUS_TXOFF
688 UARTDescs[SER_UART1].sending = false;
691 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
694 // Disable rx interrupt and tx, enable CTS interrupt
696 UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
697 sbi(EIFR, EIMSKB_CTS);
698 sbi(EIMSK, EIMSKB_CTS);
703 char c = fifo_pop(txfifo);
704 SER_UART1_BUS_TXCHAR(c);
710 #ifdef SER_UART1_BUS_TXOFF
712 * Serial port 1 TX complete interrupt handler.
714 * \sa port 0 TX complete handler.
716 SIGNAL(SIG_UART1_TRANS)
720 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
721 if (fifo_isempty(txfifo))
724 UARTDescs[SER_UART1].sending = false;
727 UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
731 #endif /* SER_UART1_BUS_TXOFF */
733 #endif // AVR_HAS_UART1
737 * Serial 0 RX complete interrupt handler.
739 * This handler is interruptible.
740 * Interrupt are reenabled as soon as recv complete interrupt is
741 * disabled. Using INTERRUPT() is troublesome when the serial
742 * is heavily loaded, because an interrupt could be retriggered
743 * when executing the handler prologue before RXCIE is disabled.
745 * \note The code that re-enables interrupts is commented out
746 * because in some nasty cases the interrupt is retriggered.
747 * This is probably due to the RXC flag being set before
748 * RXCIE is cleared. Unfortunately the RXC flag is read-only
749 * and can't be cleared by code.
751 SIGNAL(SIG_UART0_RECV)
755 /* Disable Recv complete IRQ */
756 //UCSR0B &= ~BV(RXCIE);
759 /* Should be read before UDR */
760 ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
762 /* To clear the RXC flag we must _always_ read the UDR even when we're
763 * not going to accept the incoming data, otherwise a new interrupt
764 * will occur once the handler terminates.
767 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
769 if (fifo_isfull(rxfifo))
770 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
773 fifo_push(rxfifo, c);
774 #if CONFIG_SER_HWHANDSHAKE
775 if (fifo_isfull(rxfifo))
780 /* Reenable receive complete int */
782 //UCSR0B |= BV(RXCIE);
791 * Serial 1 RX complete interrupt handler.
793 * This handler is interruptible.
794 * Interrupt are reenabled as soon as recv complete interrupt is
795 * disabled. Using INTERRUPT() is troublesome when the serial
796 * is heavily loaded, because an interrupt could be retriggered
797 * when executing the handler prologue before RXCIE is disabled.
799 * \see SIGNAL(SIG_UART0_RECV)
801 SIGNAL(SIG_UART1_RECV)
805 /* Disable Recv complete IRQ */
806 //UCSR1B &= ~BV(RXCIE);
809 /* Should be read before UDR */
810 ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
812 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
813 * not going to accept the incoming data
816 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
817 //ASSERT_VALID_FIFO(rxfifo);
819 if (UNLIKELY(fifo_isfull(rxfifo)))
820 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
823 fifo_push(rxfifo, c);
824 #if CONFIG_SER_HWHANDSHAKE
825 if (fifo_isfull(rxfifo))
829 /* Re-enable receive complete int */
831 //UCSR1B |= BV(RXCIE);
836 #endif // AVR_HAS_UART1
840 * SPI interrupt handler
844 /* Read incoming byte. */
845 if (!fifo_isfull(&ser_spi->rxfifo))
846 fifo_push(&ser_spi->rxfifo, SPDR);
850 ser_spi->status |= SERRF_RXFIFOOVERRUN;
854 if (!fifo_isempty(&ser_spi->txfifo))
855 SPDR = fifo_pop(&ser_spi->txfifo);
857 UARTDescs[SER_SPI].sending = false;