4 * Copyright (C) 2003,2004 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See devlib/README for information.
10 * \author Stefano Fedrigo <aleph@develer.com>
11 * \author Giovanni Bajo <rasky@develer.com>
13 * \brief DSP5680x CPU specific serial I/O driver
18 * Revision 1.3 2004/06/03 11:27:09 bernie
19 * Add dual-license information.
21 * Revision 1.2 2004/05/23 18:21:53 bernie
22 * Trim CVS logs and cleanup header info.
28 #include <drv/kdebug.h>
30 #include <DSP56F807.H>
32 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
33 // the serial, we need to disable the GPIO functions on them.
34 #define REG_GPIO_SERIAL REG_GPIO_E
35 #define REG_GPIO_SERIAL_MASK 0x3
37 // Check flag consistency
38 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
39 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
40 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
41 (SERRF_NOISEERROR != REG_SCI_SR_NF)
42 #error error flags do not match with register bits
47 struct SerialHardware hw;
48 struct Serial* serial;
49 volatile struct REG_SCI_STRUCT* regs;
55 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
57 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
60 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
62 regs->CR |= REG_SCI_CR_RIE | REG_SCI_CR_REIE;
65 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
67 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
70 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
72 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
75 static inline void disable_tx_irq(struct SerialHardware* _hw)
77 struct SCI* hw = (struct SCI*)_hw;
78 volatile struct REG_SCI_STRUCT* regs = hw->regs;
80 disable_tx_irq_bare(regs);
83 static inline void enable_tx_irq(struct SerialHardware* _hw)
85 struct SCI* hw = (struct SCI*)_hw;
86 volatile struct REG_SCI_STRUCT* regs = hw->regs;
88 enable_tx_irq_bare(regs);
91 static inline void enable_rx_irq(struct SerialHardware* _hw)
93 struct SCI* hw = (struct SCI*)_hw;
94 volatile struct REG_SCI_STRUCT* regs = hw->regs;
96 enable_rx_irq_bare(regs);
99 INLINE void tx_isr(struct SCI *hw)
101 volatile struct REG_SCI_STRUCT* regs = hw->regs;
103 if (fifo_isempty(&hw->serial->txfifo))
104 disable_tx_irq_bare(regs);
107 // Clear transmitter flags before sending data
109 regs->DR = fifo_pop(&hw->serial->txfifo);
113 INLINE void rx_isr(struct SCI *hw)
115 volatile struct REG_SCI_STRUCT* regs = hw->regs;
117 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
122 if (fifo_isfull(&hw->serial->rxfifo))
123 hw->serial->status |= SERRF_RXFIFOOVERRUN;
125 fifo_push(&hw->serial->rxfifo, regs->DR);
127 // Writing anything to the status register clear the
132 static void init(struct SerialHardware* _hw, struct Serial* ser)
134 struct SCI* hw = (struct SCI*)_hw;
135 volatile struct REG_SCI_STRUCT* regs = hw->regs;
137 // Clear status register (IRQ/status flags)
141 // Clear data register
144 // Set priorities for both IRQs
145 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
146 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
148 // Activate the RX error interrupts, and RX/TX transmissions
149 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
150 enable_rx_irq_bare(regs);
152 // Disable GPIO pins for TX and RX lines
153 REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK;
158 static void cleanup(struct SerialHardware* _hw)
164 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
166 struct SCI* hw = (struct SCI*)_hw;
168 // SCI has an internal 16x divider on the input clock, which comes
169 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
170 // it to calculate the period to store in the register.
171 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
174 static void setparity(struct SerialHardware* _hw, int parity)
181 static const struct SerialHardwareVT SCI_VT =
185 .setbaudrate = setbaudrate,
186 .setparity = setparity,
187 .enabletxirq = enable_tx_irq,
190 static struct SCI SCIDescs[2] =
193 .hw = { .table = &SCI_VT },
195 .irq_rx = IRQ_SCI0_RECEIVER_FULL,
196 .irq_tx = IRQ_SCI0_TRANSMITTER_READY,
200 .hw = { .table = &SCI_VT },
202 .irq_rx = IRQ_SCI1_RECEIVER_FULL,
203 .irq_tx = IRQ_SCI1_TRANSMITTER_READY,
209 void ser_hw_tx_isr_0(void);
210 void ser_hw_tx_isr_0(void)
212 #pragma interrupt warn
213 tx_isr(&SCIDescs[0]);
216 void ser_hw_rx_isr_0(void);
217 void ser_hw_rx_isr_0(void)
219 #pragma interrupt warn
220 rx_isr(&SCIDescs[0]);
223 void ser_hw_tx_isr_1(void);
224 void ser_hw_tx_isr_1(void)
226 #pragma interrupt warn
227 tx_isr(&SCIDescs[1]);
230 void ser_hw_rx_isr_1(void);
231 void ser_hw_rx_isr_1(void)
233 #pragma interrupt warn
234 rx_isr(&SCIDescs[1]);
237 struct SerialHardware* ser_hw_getdesc(int unit)
240 return &SCIDescs[unit].hw;