4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See devlib/README for information.
10 * \author Stefano Fedrigo <aleph@develer.com>
11 * \author Giovanni Bajo <rasky@develer.com>
13 * \brief DSP5680x CPU specific serial I/O driver
18 *#* Revision 1.9 2004/12/08 09:42:55 bernie
19 *#* Add support for multiplexed serial ports.
21 *#* Revision 1.8 2004/10/26 09:00:49 bernie
22 *#* Don't access serial data register twice.
24 *#* Revision 1.7 2004/10/19 08:57:15 bernie
25 *#* Bugfixes for DSP56K serial driver from scfirm.
27 *#* Revision 1.5 2004/08/25 14:12:08 rasky
28 *#* Aggiornato il comment block dei log RCS
30 *#* Revision 1.4 2004/07/30 14:27:49 rasky
31 *#* Aggiornati alcuni file DSP56k per la nuova libreria di IRQ management
33 *#* Revision 1.3 2004/06/03 11:27:09 bernie
34 *#* Add dual-license information.
36 *#* Revision 1.2 2004/05/23 18:21:53 bernie
37 *#* Trim CVS logs and cleanup header info.
45 #include <DSP56F807.h>
47 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
48 // the serial, we need to disable the GPIO functions on them.
49 #define REG_GPIO_SERIAL_0 REG_GPIO_E
50 #define REG_GPIO_SERIAL_MASK_0 0x03
52 #define REG_GPIO_SERIAL_1 REG_GPIO_D
53 #define REG_GPIO_SERIAL_MASK_1 0xC0
56 // Check flag consistency
57 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
58 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
59 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
60 (SERRF_NOISEERROR != REG_SCI_SR_NF)
61 #error error flags do not match with register bits
64 static unsigned char ser0_fifo_rx[CONFIG_SER0_FIFOSIZE_RX];
65 static unsigned char ser0_fifo_tx[CONFIG_SER0_FIFOSIZE_TX];
66 static unsigned char ser1_fifo_rx[CONFIG_SER1_FIFOSIZE_RX];
67 static unsigned char ser1_fifo_tx[CONFIG_SER1_FIFOSIZE_TX];
72 #define MAX_MULTI_GROUPS 1
74 struct Semaphore multi_sems[MAX_MULTI_GROUPS];
80 struct SerialHardware hw;
81 struct Serial* serial;
82 volatile struct REG_SCI_STRUCT* regs;
89 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
91 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
94 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
96 regs->CR |= REG_SCI_CR_RIE;
99 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
101 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
104 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
106 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
109 static inline void disable_tx_irq(struct SerialHardware* _hw)
111 struct SCI* hw = (struct SCI*)_hw;
112 volatile struct REG_SCI_STRUCT* regs = hw->regs;
114 disable_tx_irq_bare(regs);
117 static inline void disable_rx_irq(struct SerialHardware* _hw)
119 struct SCI* hw = (struct SCI*)_hw;
120 volatile struct REG_SCI_STRUCT* regs = hw->regs;
122 disable_rx_irq_bare(regs);
125 static inline void enable_tx_irq(struct SerialHardware* _hw)
127 struct SCI* hw = (struct SCI*)_hw;
128 volatile struct REG_SCI_STRUCT* regs = hw->regs;
130 enable_tx_irq_bare(regs);
133 static inline void enable_rx_irq(struct SerialHardware* _hw)
135 struct SCI* hw = (struct SCI*)_hw;
136 volatile struct REG_SCI_STRUCT* regs = hw->regs;
138 enable_rx_irq_bare(regs);
141 static void tx_isr(const struct SCI *hw)
143 #pragma interrupt warn
144 volatile struct REG_SCI_STRUCT* regs = hw->regs;
146 if (fifo_isempty(&hw->serial->txfifo))
147 disable_tx_irq_bare(regs);
150 // Clear transmitter flags before sending data
152 regs->DR = fifo_pop(&hw->serial->txfifo);
156 static void rx_isr(const struct SCI *hw)
158 #pragma interrupt warn
159 volatile struct REG_SCI_STRUCT* regs = hw->regs;
162 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
168 * Serial IRQ can happen for two reason: data ready (RDRF) or overrun (OR)
169 * If the data is ready, we need to fetch it from the data register or
170 * the interrupt will retrigger immediatly. In case of overrun, instead,
171 * the value of the data register is meaningless.
173 if (regs->SR & REG_SCI_SR_RDRF)
175 unsigned char data = regs->DR;
177 if (fifo_isfull(&hw->serial->rxfifo))
178 hw->serial->status |= SERRF_RXFIFOOVERRUN;
180 fifo_push(&hw->serial->rxfifo, data);
183 // Writing anything to the status register clear the error bits.
187 static void init(struct SerialHardware* _hw, struct Serial* ser)
189 struct SCI* hw = (struct SCI*)_hw;
190 volatile struct REG_SCI_STRUCT* regs = hw->regs;
192 // Clear status register (IRQ/status flags)
196 // Clear data register
199 // Install the handlers and set priorities for both IRQs
200 irq_install(hw->irq_tx, (isr_t)tx_isr, hw);
201 irq_install(hw->irq_rx, (isr_t)rx_isr, hw);
202 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
203 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
205 // Activate the RX error interrupts, and RX/TX transmissions
206 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
207 enable_rx_irq_bare(regs);
209 // Disable GPIO pins for TX and RX lines
210 // \todo this should be divided into serial 0 and 1
211 REG_GPIO_SERIAL_0->PER |= REG_GPIO_SERIAL_MASK_0;
212 REG_GPIO_SERIAL_1->PER |= REG_GPIO_SERIAL_MASK_1;
217 static void cleanup(struct SerialHardware* _hw)
219 struct SCI* hw = (struct SCI*)_hw;
221 // Wait until we finish sending everything
222 ser_drain(hw->serial);
223 ser_purge(hw->serial);
225 // Uninstall the ISRs
228 irq_uninstall(hw->irq_tx);
229 irq_uninstall(hw->irq_rx);
232 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
234 struct SCI* hw = (struct SCI*)_hw;
236 // SCI has an internal 16x divider on the input clock, which comes
237 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
238 // it to calculate the period to store in the register.
239 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
242 static void setparity(struct SerialHardware* _hw, int parity)
251 static void multi_init(void)
253 static bool flag = false;
259 for (i = 0; i < MAX_MULTI_GROUPS; ++i)
260 sem_init(&multi_sems[i]);
264 static void init_lock(struct SerialHardware* _hw, struct Serial *ser)
266 struct SCI* hw = (struct SCI*)_hw;
268 // Initialize the multi engine (if needed)
271 // Acquire the lock of the semaphore for this group
272 ASSERT(hw->num_group >= 0);
273 ASSERT(hw->num_group < MAX_MULTI_GROUPS);
274 sem_obtain(&multi_sems[hw->num_group]);
276 // Do a hardware switch to the given serial
277 ser_hw_switch(hw->num_group, hw->id);
282 static void cleanup_unlock(struct SerialHardware* _hw)
284 struct SCI* hw = (struct SCI*)_hw;
288 sem_release(&multi_sems[hw->num_group]);
291 #endif /* CONFIG_SER_MULTI */
294 static const struct SerialHardwareVT SCI_VT =
298 .setbaudrate = setbaudrate,
299 .setparity = setparity,
300 .enabletxirq = enable_tx_irq,
304 static const struct SerialHardwareVT SCI_MULTI_VT =
307 .cleanup = cleanup_unlock,
308 .setbaudrate = setbaudrate,
309 .setparity = setparity,
310 .enabletxirq = enable_tx_irq,
312 #endif /* CONFIG_SER_MULTI */
314 #define SCI_DESC_NORMAL(hwch) \
319 .rxbuffer = ser ## hwch ## _fifo_rx, \
320 .txbuffer = ser ## hwch ## _fifo_tx, \
321 .rxbuffer_size = countof(ser ## hwch ## _fifo_rx), \
322 .txbuffer_size = countof(ser ## hwch ## _fifo_tx), \
324 .regs = ®_SCI[hwch], \
325 .irq_rx = IRQ_SCI ## hwch ## _RECEIVER_FULL, \
326 .irq_tx = IRQ_SCI ## hwch ## _TRANSMITTER_READY, \
333 #define SCI_DESC_MULTI(hwch, group_, id_) \
337 .table = &SCI_MULTI_VT, \
338 .rxbuffer = ser ## hwch ## _fifo_rx, \
339 .txbuffer = ser ## hwch ## _fifo_tx, \
340 .rxbuffer_size = countof(ser ## hwch ## _fifo_rx), \
341 .txbuffer_size = countof(ser ## hwch ## _fifo_tx), \
343 .regs = ®_SCI[hwch], \
344 .irq_rx = IRQ_SCI ## hwch ## _RECEIVER_FULL, \
345 .irq_tx = IRQ_SCI ## hwch ## _TRANSMITTER_READY, \
346 .num_group = group_, \
350 #endif /* CONFIG_SER_MULTI */
352 // \todo Move this into hw.h, with a little preprocessor magic
353 static struct SCI SCIDescs[] =
356 SCI_DESC_MULTI(1, 0, 0),
357 SCI_DESC_MULTI(1, 0, 1),
360 struct SerialHardware* ser_hw_getdesc(int unit)
362 ASSERT(unit < countof(SCIDescs));
363 return &SCIDescs[unit].hw;