4 * Copyright (C) 2003,2004 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See devlib/README for information.
10 * \author Stefano Fedrigo <aleph@develer.com>
11 * \author Giovanni Bajo <rasky@develer.com>
13 * \brief DSP5680x CPU specific serial I/O driver
18 *#* Revision 1.5 2004/08/25 14:12:08 rasky
19 *#* Aggiornato il comment block dei log RCS
21 *#* Revision 1.4 2004/07/30 14:27:49 rasky
22 *#* Aggiornati alcuni file DSP56k per la nuova libreria di IRQ management
24 *#* Revision 1.3 2004/06/03 11:27:09 bernie
25 *#* Add dual-license information.
27 *#* Revision 1.2 2004/05/23 18:21:53 bernie
28 *#* Trim CVS logs and cleanup header info.
34 #include <drv/kdebug.h>
37 #include <DSP56F807.H>
39 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
40 // the serial, we need to disable the GPIO functions on them.
41 #define REG_GPIO_SERIAL REG_GPIO_E
42 #define REG_GPIO_SERIAL_MASK 0x3
44 // Check flag consistency
45 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
46 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
47 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
48 (SERRF_NOISEERROR != REG_SCI_SR_NF)
49 #error error flags do not match with register bits
54 struct SerialHardware hw;
55 struct Serial* serial;
56 volatile struct REG_SCI_STRUCT* regs;
61 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
63 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
66 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
68 regs->CR |= REG_SCI_CR_RIE | REG_SCI_CR_REIE;
71 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
73 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
76 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
78 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
81 static inline void disable_tx_irq(struct SerialHardware* _hw)
83 struct SCI* hw = (struct SCI*)_hw;
84 volatile struct REG_SCI_STRUCT* regs = hw->regs;
86 disable_tx_irq_bare(regs);
89 static inline void enable_tx_irq(struct SerialHardware* _hw)
91 struct SCI* hw = (struct SCI*)_hw;
92 volatile struct REG_SCI_STRUCT* regs = hw->regs;
94 enable_tx_irq_bare(regs);
97 static inline void enable_rx_irq(struct SerialHardware* _hw)
99 struct SCI* hw = (struct SCI*)_hw;
100 volatile struct REG_SCI_STRUCT* regs = hw->regs;
102 enable_rx_irq_bare(regs);
105 static void tx_isr(const struct SCI *hw)
107 #pragma interrupt warn
108 volatile struct REG_SCI_STRUCT* regs = hw->regs;
110 if (fifo_isempty(&hw->serial->txfifo))
111 disable_tx_irq_bare(regs);
114 // Clear transmitter flags before sending data
116 regs->DR = fifo_pop(&hw->serial->txfifo);
120 static void rx_isr(const struct SCI *hw)
122 #pragma interrupt warn
123 volatile struct REG_SCI_STRUCT* regs = hw->regs;
125 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
130 if (fifo_isfull(&hw->serial->rxfifo))
131 hw->serial->status |= SERRF_RXFIFOOVERRUN;
133 fifo_push(&hw->serial->rxfifo, regs->DR);
135 // Writing anything to the status register clear the
140 static void init(struct SerialHardware* _hw, struct Serial* ser)
142 struct SCI* hw = (struct SCI*)_hw;
143 volatile struct REG_SCI_STRUCT* regs = hw->regs;
145 // Clear status register (IRQ/status flags)
149 // Clear data register
152 // Install the handlers and set priorities for both IRQs
153 irq_install(hw->irq_tx, (isr_t)tx_isr, hw);
154 irq_install(hw->irq_rx, (isr_t)rx_isr, hw);
155 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
156 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
158 // Activate the RX error interrupts, and RX/TX transmissions
159 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
160 enable_rx_irq_bare(regs);
162 // Disable GPIO pins for TX and RX lines
163 REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK;
168 static void cleanup(struct SerialHardware* _hw)
174 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
176 struct SCI* hw = (struct SCI*)_hw;
178 // SCI has an internal 16x divider on the input clock, which comes
179 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
180 // it to calculate the period to store in the register.
181 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
184 static void setparity(struct SerialHardware* _hw, int parity)
191 static const struct SerialHardwareVT SCI_VT =
195 .setbaudrate = setbaudrate,
196 .setparity = setparity,
197 .enabletxirq = enable_tx_irq,
200 static struct SCI SCIDescs[2] =
203 .hw = { .table = &SCI_VT },
205 .irq_rx = IRQ_SCI0_RECEIVER_FULL,
206 .irq_tx = IRQ_SCI0_TRANSMITTER_READY,
210 .hw = { .table = &SCI_VT },
212 .irq_rx = IRQ_SCI1_RECEIVER_FULL,
213 .irq_tx = IRQ_SCI1_TRANSMITTER_READY,
218 struct SerialHardware* ser_hw_getdesc(int unit)
221 return &SCIDescs[unit].hw;