4 * Copyright (C) 2003,2004 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See devlib/README for information.
10 * \author Stefano Fedrigo <aleph@develer.com>
11 * \author Giovanni Bajo <rasky@develer.com>
13 * \brief DSP5680x CPU specific serial I/O driver
18 *#* Revision 1.6 2004/10/03 20:43:22 bernie
19 *#* Import changes from sc/firmware.
21 *#* Revision 1.5 2004/08/25 14:12:08 rasky
22 *#* Aggiornato il comment block dei log RCS
24 *#* Revision 1.4 2004/07/30 14:27:49 rasky
25 *#* Aggiornati alcuni file DSP56k per la nuova libreria di IRQ management
27 *#* Revision 1.3 2004/06/03 11:27:09 bernie
28 *#* Add dual-license information.
30 *#* Revision 1.2 2004/05/23 18:21:53 bernie
31 *#* Trim CVS logs and cleanup header info.
39 #include <DSP56F807.h>
41 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
42 // the serial, we need to disable the GPIO functions on them.
43 #define REG_GPIO_SERIAL REG_GPIO_E
44 #define REG_GPIO_SERIAL_MASK 0x3
46 // Check flag consistency
47 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
48 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
49 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
50 (SERRF_NOISEERROR != REG_SCI_SR_NF)
51 #error error flags do not match with register bits
56 struct SerialHardware hw;
57 struct Serial* serial;
58 volatile struct REG_SCI_STRUCT* regs;
63 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
65 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
68 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
70 regs->CR |= REG_SCI_CR_RIE | REG_SCI_CR_REIE;
73 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
75 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
78 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
80 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
83 static inline void disable_tx_irq(struct SerialHardware* _hw)
85 struct SCI* hw = (struct SCI*)_hw;
86 volatile struct REG_SCI_STRUCT* regs = hw->regs;
88 disable_tx_irq_bare(regs);
91 static inline void enable_tx_irq(struct SerialHardware* _hw)
93 struct SCI* hw = (struct SCI*)_hw;
94 volatile struct REG_SCI_STRUCT* regs = hw->regs;
96 enable_tx_irq_bare(regs);
99 static inline void enable_rx_irq(struct SerialHardware* _hw)
101 struct SCI* hw = (struct SCI*)_hw;
102 volatile struct REG_SCI_STRUCT* regs = hw->regs;
104 enable_rx_irq_bare(regs);
107 static void tx_isr(const struct SCI *hw)
109 #pragma interrupt warn
110 volatile struct REG_SCI_STRUCT* regs = hw->regs;
112 if (fifo_isempty(&hw->serial->txfifo))
113 disable_tx_irq_bare(regs);
116 // Clear transmitter flags before sending data
118 regs->DR = fifo_pop(&hw->serial->txfifo);
122 static void rx_isr(const struct SCI *hw)
124 #pragma interrupt warn
125 volatile struct REG_SCI_STRUCT* regs = hw->regs;
127 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
132 if (fifo_isfull(&hw->serial->rxfifo))
133 hw->serial->status |= SERRF_RXFIFOOVERRUN;
135 fifo_push(&hw->serial->rxfifo, regs->DR);
137 // Writing anything to the status register clear the
142 static void init(struct SerialHardware* _hw, struct Serial* ser)
144 struct SCI* hw = (struct SCI*)_hw;
145 volatile struct REG_SCI_STRUCT* regs = hw->regs;
147 // Clear status register (IRQ/status flags)
151 // Clear data register
154 // Install the handlers and set priorities for both IRQs
155 irq_install(hw->irq_tx, (isr_t)tx_isr, hw);
156 irq_install(hw->irq_rx, (isr_t)rx_isr, hw);
157 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
158 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
160 // Activate the RX error interrupts, and RX/TX transmissions
161 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
162 enable_rx_irq_bare(regs);
164 // Disable GPIO pins for TX and RX lines
165 REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK;
170 static void cleanup(struct SerialHardware* _hw)
176 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
178 struct SCI* hw = (struct SCI*)_hw;
180 // SCI has an internal 16x divider on the input clock, which comes
181 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
182 // it to calculate the period to store in the register.
183 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
186 static void setparity(struct SerialHardware* _hw, int parity)
193 static const struct SerialHardwareVT SCI_VT =
197 .setbaudrate = setbaudrate,
198 .setparity = setparity,
199 .enabletxirq = enable_tx_irq,
202 static struct SCI SCIDescs[2] =
205 .hw = { .table = &SCI_VT },
207 .irq_rx = IRQ_SCI0_RECEIVER_FULL,
208 .irq_tx = IRQ_SCI0_TRANSMITTER_READY,
212 .hw = { .table = &SCI_VT },
214 .irq_rx = IRQ_SCI1_RECEIVER_FULL,
215 .irq_tx = IRQ_SCI1_TRANSMITTER_READY,
220 struct SerialHardware* ser_hw_getdesc(int unit)
223 return &SCIDescs[unit].hw;