4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * This file is part of DevLib - See devlib/README for information.
10 * \author Stefano Fedrigo <aleph@develer.com>
11 * \author Giovanni Bajo <rasky@develer.com>
13 * \brief DSP5680x CPU specific serial I/O driver
18 *#* Revision 1.7 2004/10/19 08:57:15 bernie
19 *#* Bugfixes for DSP56K serial driver from scfirm.
21 *#* Revision 1.5 2004/08/25 14:12:08 rasky
22 *#* Aggiornato il comment block dei log RCS
24 *#* Revision 1.4 2004/07/30 14:27:49 rasky
25 *#* Aggiornati alcuni file DSP56k per la nuova libreria di IRQ management
27 *#* Revision 1.3 2004/06/03 11:27:09 bernie
28 *#* Add dual-license information.
30 *#* Revision 1.2 2004/05/23 18:21:53 bernie
31 *#* Trim CVS logs and cleanup header info.
39 #include <DSP56F807.h>
41 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
42 // the serial, we need to disable the GPIO functions on them.
43 #define REG_GPIO_SERIAL REG_GPIO_E
44 #define REG_GPIO_SERIAL_MASK 0x3
46 // Check flag consistency
47 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
48 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
49 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
50 (SERRF_NOISEERROR != REG_SCI_SR_NF)
51 #error error flags do not match with register bits
54 static unsigned char ser0_fifo_rx[CONFIG_SER0_FIFOSIZE_RX];
55 static unsigned char ser0_fifo_tx[CONFIG_SER0_FIFOSIZE_TX];
56 static unsigned char ser1_fifo_rx[CONFIG_SER1_FIFOSIZE_RX];
57 static unsigned char ser1_fifo_tx[CONFIG_SER1_FIFOSIZE_TX];
61 struct SerialHardware hw;
62 struct Serial* serial;
63 volatile struct REG_SCI_STRUCT* regs;
68 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
70 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
73 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
75 regs->CR |= REG_SCI_CR_RIE;
78 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
80 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
83 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
85 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
88 static inline void disable_tx_irq(struct SerialHardware* _hw)
90 struct SCI* hw = (struct SCI*)_hw;
91 volatile struct REG_SCI_STRUCT* regs = hw->regs;
93 disable_tx_irq_bare(regs);
96 static inline void enable_tx_irq(struct SerialHardware* _hw)
98 struct SCI* hw = (struct SCI*)_hw;
99 volatile struct REG_SCI_STRUCT* regs = hw->regs;
101 enable_tx_irq_bare(regs);
104 static inline void enable_rx_irq(struct SerialHardware* _hw)
106 struct SCI* hw = (struct SCI*)_hw;
107 volatile struct REG_SCI_STRUCT* regs = hw->regs;
109 enable_rx_irq_bare(regs);
112 static void tx_isr(const struct SCI *hw)
114 #pragma interrupt warn
115 volatile struct REG_SCI_STRUCT* regs = hw->regs;
117 if (fifo_isempty(&hw->serial->txfifo))
118 disable_tx_irq_bare(regs);
121 // Clear transmitter flags before sending data
123 regs->DR = fifo_pop(&hw->serial->txfifo);
127 static void rx_isr(const struct SCI *hw)
129 #pragma interrupt warn
130 volatile struct REG_SCI_STRUCT* regs = hw->regs;
133 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
139 * Serial IRQ can happen for two reason: data ready (RDRF) or overrun (OR)
140 * If the data is ready, we need to fetch it from the data register or
141 * the interrupt will retrigger immediatly. In case of overrun, instead,
142 * the value of the data register is meaningless.
144 if (regs->SR & REG_SCI_SR_RDRF)
146 unsigned char data = regs->DR;
148 if (fifo_isfull(&hw->serial->rxfifo))
149 if (fifo_isfull(&hw->serial->rxfifo))
150 hw->serial->status |= SERRF_RXFIFOOVERRUN;
152 fifo_push(&hw->serial->rxfifo, regs->DR);
154 // Writing anything to the status register clear the error bits.
158 static void init(struct SerialHardware* _hw, struct Serial* ser)
160 struct SCI* hw = (struct SCI*)_hw;
161 volatile struct REG_SCI_STRUCT* regs = hw->regs;
163 // Clear status register (IRQ/status flags)
167 // Clear data register
170 // Install the handlers and set priorities for both IRQs
171 irq_install(hw->irq_tx, (isr_t)tx_isr, hw);
172 irq_install(hw->irq_rx, (isr_t)rx_isr, hw);
173 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
174 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
176 // Activate the RX error interrupts, and RX/TX transmissions
177 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
178 enable_rx_irq_bare(regs);
180 // Disable GPIO pins for TX and RX lines
181 REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK;
186 static void cleanup(struct SerialHardware* _hw)
192 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
194 struct SCI* hw = (struct SCI*)_hw;
196 // SCI has an internal 16x divider on the input clock, which comes
197 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
198 // it to calculate the period to store in the register.
199 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
202 static void setparity(struct SerialHardware* _hw, int parity)
209 static const struct SerialHardwareVT SCI_VT =
213 .setbaudrate = setbaudrate,
214 .setparity = setparity,
215 .enabletxirq = enable_tx_irq,
218 static struct SCI SCIDescs[2] =
224 .rxbuffer = ser0_fifo_rx,
225 .txbuffer = ser0_fifo_tx,
226 .rxbuffer_size = countof(ser0_fifo_rx),
227 .txbuffer_size = countof(ser0_fifo_tx),
230 .irq_rx = IRQ_SCI0_RECEIVER_FULL,
231 .irq_tx = IRQ_SCI0_TRANSMITTER_READY,
238 .rxbuffer = ser1_fifo_rx,
239 .txbuffer = ser1_fifo_tx,
240 .rxbuffer_size = countof(ser1_fifo_rx),
241 .txbuffer_size = countof(ser1_fifo_tx),
244 .irq_rx = IRQ_SCI1_RECEIVER_FULL,
245 .irq_tx = IRQ_SCI1_TRANSMITTER_READY,
250 struct SerialHardware* ser_hw_getdesc(int unit)
253 return &SCIDescs[unit].hw;