3 * Copyright (C) 2003 Develer S.r.l. (http://www.develer.com/)
8 * \author Stefano Fedrigo <aleph@develer.com>
10 * \brief DSP5680x CPU specific serial I/O driver
13 #include <DSP56F807.H>
14 #include <drv/kdebug.h>
19 // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use
20 // the serial, we need to disable the GPIO functions on them.
21 #define REG_GPIO_SERIAL REG_GPIO_E
22 #define REG_GPIO_SERIAL_MASK 0x3
24 // Check flag consistency
25 #if (SERRF_PARITYERROR != REG_SCI_SR_PF) || \
26 (SERRF_RXSROVERRUN != REG_SCI_SR_OR) || \
27 (SERRF_FRAMEERROR != REG_SCI_SR_FE) || \
28 (SERRF_NOISEERROR != REG_SCI_SR_NF)
29 #error error flags do not match with register bits
34 struct SerialHardware hw;
35 struct Serial* serial;
36 volatile struct REG_SCI_STRUCT* regs;
42 static inline void enable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
44 regs->CR |= REG_SCI_CR_TEIE | REG_SCI_CR_TIIE;
47 static inline void enable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
49 regs->CR |= REG_SCI_CR_RIE | REG_SCI_CR_REIE;
52 static inline void disable_tx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
54 regs->CR &= ~(REG_SCI_CR_TEIE | REG_SCI_CR_TIIE);
57 static inline void disable_rx_irq_bare(volatile struct REG_SCI_STRUCT* regs)
59 regs->CR &= ~(REG_SCI_CR_RIE | REG_SCI_CR_REIE);
62 static inline void disable_tx_irq(struct SerialHardware* _hw)
64 struct SCI* hw = (struct SCI*)_hw;
65 volatile struct REG_SCI_STRUCT* regs = hw->regs;
67 disable_tx_irq_bare(regs);
70 static inline void enable_tx_irq(struct SerialHardware* _hw)
72 struct SCI* hw = (struct SCI*)_hw;
73 volatile struct REG_SCI_STRUCT* regs = hw->regs;
75 enable_tx_irq_bare(regs);
78 static inline void enable_rx_irq(struct SerialHardware* _hw)
80 struct SCI* hw = (struct SCI*)_hw;
81 volatile struct REG_SCI_STRUCT* regs = hw->regs;
83 enable_rx_irq_bare(regs);
86 INLINE void tx_isr(struct SCI *hw)
88 volatile struct REG_SCI_STRUCT* regs = hw->regs;
90 if (fifo_isempty(&hw->serial->txfifo))
91 disable_tx_irq_bare(regs);
94 // Clear transmitter flags before sending data
96 regs->DR = fifo_pop(&hw->serial->txfifo);
100 INLINE void rx_isr(struct SCI *hw)
102 volatile struct REG_SCI_STRUCT* regs = hw->regs;
104 hw->serial->status |= regs->SR & (SERRF_PARITYERROR |
109 if (fifo_isfull(&hw->serial->rxfifo))
110 hw->serial->status |= SERRF_RXFIFOOVERRUN;
112 fifo_push(&hw->serial->rxfifo, regs->DR);
114 // Writing anything to the status register clear the
119 static void init(struct SerialHardware* _hw, struct Serial* ser)
121 struct SCI* hw = (struct SCI*)_hw;
122 volatile struct REG_SCI_STRUCT* regs = hw->regs;
124 // Clear status register (IRQ/status flags)
128 // Clear data register
131 // Set priorities for both IRQs
132 irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX);
133 irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX);
135 // Activate the RX error interrupts, and RX/TX transmissions
136 regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE;
137 enable_rx_irq_bare(regs);
139 // Disable GPIO pins for TX and RX lines
140 REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK;
145 static void cleanup(struct SerialHardware* _hw)
151 static void setbaudrate(struct SerialHardware* _hw, unsigned long rate)
153 struct SCI* hw = (struct SCI*)_hw;
155 // SCI has an internal 16x divider on the input clock, which comes
156 // from the IPbus (see the scheme in user manual, 12.7.3). We apply
157 // it to calculate the period to store in the register.
158 hw->regs->BR = (IPBUS_FREQ + rate * 8ul) / (rate * 16ul);
161 static void setparity(struct SerialHardware* _hw, int parity)
168 static const struct SerialHardwareVT SCI_VT =
172 .setbaudrate = setbaudrate,
173 .setparity = setparity,
174 .enabletxirq = enable_tx_irq,
177 static struct SCI SCIDescs[2] =
180 .hw = { .table = &SCI_VT },
182 .irq_rx = IRQ_SCI0_RECEIVER_FULL,
183 .irq_tx = IRQ_SCI0_TRANSMITTER_READY,
187 .hw = { .table = &SCI_VT },
189 .irq_rx = IRQ_SCI1_RECEIVER_FULL,
190 .irq_tx = IRQ_SCI1_TRANSMITTER_READY,
196 void ser_hw_tx_isr_0(void);
197 void ser_hw_tx_isr_0(void)
199 #pragma interrupt warn
200 tx_isr(&SCIDescs[0]);
203 void ser_hw_rx_isr_0(void);
204 void ser_hw_rx_isr_0(void)
206 #pragma interrupt warn
207 rx_isr(&SCIDescs[0]);
210 void ser_hw_tx_isr_1(void);
211 void ser_hw_tx_isr_1(void)
213 #pragma interrupt warn
214 tx_isr(&SCIDescs[1]);
217 void ser_hw_rx_isr_1(void);
218 void ser_hw_rx_isr_1(void)
220 #pragma interrupt warn
221 rx_isr(&SCIDescs[1]);
224 struct SerialHardware* ser_hw_getdesc(int unit)
227 return &SCIDescs[unit].hw;