4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 UART interface driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include <drv/gpio_lm3s.h>
40 #include <drv/ser_p.h>
42 #include <drv/irq_cm3.h>
43 #include "cfg/cfg_ser.h"
46 /* From the high-level serial driver */
47 extern struct Serial *ser_handles[SER_CNT];
51 struct SerialHardware hw;
57 /* Forward declaration */
58 static struct CM3Serial UARTDesc[SER_CNT];
60 /* GPIO descriptor for UART pins */
65 /* GPIO base address register */
71 /* Table to retrieve GPIO pins configuration to work as UART pins */
72 static const struct gpio_uart_info gpio_uart[SER_CNT] =
76 .base = GPIO_PORTA_BASE,
77 .pins = BV(1) | BV(0),
78 .sysctl = SYSCTL_RCGC2_GPIOA,
82 .base = GPIO_PORTD_BASE,
83 .pins = BV(3) | BV(2),
84 .sysctl = SYSCTL_RCGC2_GPIOD,
88 .base = GPIO_PORTG_BASE,
89 .pins = BV(1) | BV(0),
90 .sysctl = SYSCTL_RCGC2_GPIOG,
94 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
99 if (baud * 16 > CPU_FREQ)
104 div = (CPU_FREQ * 8 / baud + 1) / 2;
106 lm3s_uartDisable(base);
108 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
110 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
111 /* Set the baud rate */
112 HWREG(base + UART_O_IBRD) = div / 64;
113 HWREG(base + UART_O_FBRD) = div % 64;
114 lm3s_uartClear(base);
115 lm3s_uartEnable(base);
118 void lm3s_uartSetParity(uint32_t base, int parity)
120 /* Set 8-bit word, one stop bit by default */
121 uint32_t config = UART_LCRH_WLEN_8;
125 case SER_PARITY_NONE:
128 config |= UART_LCRH_PEN;
130 case SER_PARITY_EVEN:
131 config |= UART_LCRH_EPS | UART_LCRH_PEN;
137 lm3s_uartDisable(base);
138 HWREG(base + UART_O_LCRH) = config;
139 lm3s_uartClear(base);
140 lm3s_uartEnable(base);
143 void lm3s_uartInit(int port)
145 uint32_t reg_clock, base;
147 ASSERT(port >= 0 && port < SER_CNT);
149 base = UARTDesc[port].base;
150 reg_clock = 1 << port;
152 /* Enable the peripheral clock */
153 SYSCTL_RCGC1_R |= reg_clock;
154 SYSCTL_RCGC2_R |= gpio_uart[port].sysctl;
157 /* Configure GPIO pins to work as UART pins */
158 lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins,
159 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
161 /* Set serial param: 115.200 bps, no parity */
162 lm3s_uartSetBaudRate(base, 115200);
163 lm3s_uartSetParity(base, SER_PARITY_NONE);
166 static bool tx_sending(struct SerialHardware *_hw)
168 struct CM3Serial *hw = (struct CM3Serial *)_hw;
172 static void uart_irq_rx(int port)
174 struct FIFOBuffer *rxfifo = &ser_handles[port]->rxfifo;
175 uint32_t base = UARTDesc[port].base;
178 while (lm3s_uartRxReady(base))
180 c = HWREG(base + UART_O_DR);
181 if (fifo_isfull(rxfifo))
182 ser_handles[port]->status |= SERRF_RXFIFOOVERRUN;
184 fifo_push(rxfifo, c);
188 static void uart_irq_tx(int port)
190 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;
191 uint32_t base = UARTDesc[port].base;
193 while (lm3s_uartTxReady(base))
195 if (fifo_isempty(txfifo))
198 * Disable TX empty interrupts if there're no more
199 * characters to transmit.
201 HWREG(base + UART_O_IM) &= ~UART_IM_TXIM;
202 UARTDesc[port].sending = false;
205 HWREG(base + UART_O_DR) = fifo_pop(txfifo);
209 static void uart_common_irq_handler(int port)
211 uint32_t base = UARTDesc[port].base;
214 /* Read and clear the IRQ status */
215 status = HWREG(base + UART_O_RIS);
217 /* Process the IRQ */
218 if (status & (UART_RIS_RXRIS | UART_RIS_RTRIS))
220 if (status & UART_RIS_TXRIS)
224 static void lm3s_uartIRQEnable(int port, sysirq_handler_t handler)
226 uint32_t base = UARTDesc[port].base;
227 sysirq_t irq = UARTDesc[port].irq;
229 /* Register the IRQ handler */
230 sysirq_setHandler(irq, handler);
231 /* Enable RX interrupt in the UART interrupt mask register */
232 HWREG(base + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
235 static void lm3s_uartIRQDisable(int port)
237 uint32_t base = UARTDesc[port].base;
239 HWREG(base + UART_O_IM) &=
240 ~(UART_IM_TXIM | UART_IM_RXIM | UART_IM_RTIM);
243 /* UART class definition */
244 #define UART_PORT(port) \
245 /* UART TX and RX buffers */ \
246 static unsigned char \
247 uart ## port ## _txbuffer[CONFIG_UART ## port ## _TXBUFSIZE]; \
248 static unsigned char \
249 uart ## port ## _rxbuffer[CONFIG_UART ## port ## _RXBUFSIZE]; \
251 /* UART interrupt handler */ \
252 static DECLARE_ISR(uart ## port ## _irq_handler) \
254 uart_common_irq_handler(port); \
257 /* UART public methods */ \
259 uart ## port ## _txStart(struct SerialHardware *_hw) \
261 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo; \
262 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
266 lm3s_uartPutChar(UART ## port ## _BASE, fifo_pop(txfifo)); \
267 if (!fifo_isempty(txfifo)) \
269 HWREG(UART ## port ## _BASE + UART_O_IM) |= \
271 hw->sending = true; \
276 uart ## port ## _setbaudrate(UNUSED_ARG(struct SerialHardware *, hw), \
277 unsigned long baud) \
279 lm3s_uartSetBaudRate(UART ## port ## _BASE, baud); \
283 uart ## port ## _setparity(UNUSED_ARG(struct SerialHardware *, hw), \
286 lm3s_uartSetParity(UART ## port ## _BASE, parity); \
290 uart ## port ## _cleanup(struct SerialHardware *_hw) \
292 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
294 hw->sending = false; \
295 lm3s_uartIRQDisable(port); \
296 lm3s_uartClear(UART ## port ## _BASE); \
297 lm3s_uartDisable(UART ## port ## _BASE); \
301 uart ## port ## _init(UNUSED_ARG(struct SerialHardware *, hw), \
302 UNUSED_ARG(struct Serial *, ser)) \
304 lm3s_uartInit(port); \
305 lm3s_uartEnable(UART ## port ## _BASE); \
306 lm3s_uartIRQEnable(port, uart ## port ## _irq_handler); \
309 /* UART operations */ \
310 static const struct SerialHardwareVT UART ## port ## _VT = \
312 .init = uart ## port ## _init, \
313 .cleanup = uart ## port ## _cleanup, \
314 .setBaudrate = uart ## port ## _setbaudrate, \
315 .setParity = uart ## port ## _setparity, \
316 .txStart = uart ## port ## _txStart, \
317 .txSending = tx_sending, \
320 /* UART port instances */
325 static struct CM3Serial UARTDesc[SER_CNT] =
330 .txbuffer = uart0_txbuffer,
331 .rxbuffer = uart0_rxbuffer,
332 .txbuffer_size = sizeof(uart0_txbuffer),
333 .rxbuffer_size = sizeof(uart0_rxbuffer),
342 .txbuffer = uart1_txbuffer,
343 .rxbuffer = uart1_rxbuffer,
344 .txbuffer_size = sizeof(uart1_txbuffer),
345 .rxbuffer_size = sizeof(uart1_rxbuffer),
354 .txbuffer = uart2_txbuffer,
355 .rxbuffer = uart2_rxbuffer,
356 .txbuffer_size = sizeof(uart2_txbuffer),
357 .rxbuffer_size = sizeof(uart2_rxbuffer),
365 struct SerialHardware *ser_hw_getdesc(int port)
367 ASSERT(port >= 0 && port < SER_CNT);
368 return &UARTDesc[port].hw;