4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@develer.com>
6 * This file is part of DevLib - See devlib/README for information.
11 * \author Bernardo Innocenti <bernie@develer.com>
13 * \brief Low-level timer module for AVR
18 *#* Revision 1.20 2004/11/16 20:59:46 bernie
19 *#* Include <avr/io.h> explicitly.
21 *#* Revision 1.19 2004/10/19 08:56:41 bernie
22 *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong.
24 *#* Revision 1.18 2004/09/20 03:31:03 bernie
25 *#* Fix racy racy code.
27 *#* Revision 1.17 2004/09/14 21:07:09 bernie
28 *#* Include hw.h explicitly.
30 *#* Revision 1.16 2004/09/06 21:49:26 bernie
31 *#* CONFIG_TIMER_STROBE: be tolerant with missing optional macro.
33 *#* Revision 1.15 2004/08/25 14:12:08 rasky
34 *#* Aggiornato il comment block dei log RCS
36 *#* Revision 1.14 2004/08/24 16:27:01 bernie
37 *#* Add missing headers.
39 *#* Revision 1.13 2004/08/24 14:30:11 bernie
40 *#* Use new-style config macros for drv/timer.c
42 *#* Revision 1.12 2004/08/10 06:59:45 bernie
43 *#* CONFIG_TIMER_STROBE: Define no-op default macros.
45 *#* Revision 1.11 2004/08/03 15:53:17 aleph
48 *#* Revision 1.10 2004/08/02 20:20:29 aleph
49 *#* Merge from project_ks
51 *#* Revision 1.9 2004/07/22 02:01:14 bernie
52 *#* Use TIMER_PRESCALER consistently.
54 #ifndef DRV_TIMER_AVR_H
55 #define DRV_TIMER_AVR_H
57 #include <arch_config.h> // ARCH_BOARD_KC
60 #include <avr/signal.h>
63 #if defined(ARCH_BOARD_KC) && (ARCH & ARCH_BOARD_KC)
69 * Values for CONFIG_TIMER.
71 * Select which hardware timer interrupt to use for system clock and softtimers.
72 * \note The timer 1 overflow mode set the timer as a 24 kHz PWM.
74 #define TIMER_ON_OUTPUT_COMPARE0 1
75 #define TIMER_ON_OVERFLOW1 2
76 #define TIMER_ON_OUTPUT_COMPARE2 3
79 /* Not needed, IRQ timer flag cleared automatically */
80 #define timer_hw_irq() do {} while (0)
82 #define TIMER_PRESCALER 64
85 * System timer: additional division after the prescaler
86 * 12288000 / 64 / 192 (0..191) = 1 ms
88 #define OCR_DIVISOR (CLOCK_FREQ / TIMER_PRESCALER / TICKS_PER_SEC - 1) /* 191 */
90 /*! HW dependent timer initialization */
91 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
93 //! Type of time expressed in ticks of the hardware high-precision timer
94 typedef uint8_t hptime_t;
96 static void timer_hw_init(void)
99 DISABLE_IRQSAVE(flags);
101 /* Reset Timer flags */
102 TIFR = BV(OCF0) | BV(TOV0);
104 /* Setup Timer/Counter interrupt */
105 ASSR = 0x00; /* Internal system clock */
106 TCCR0 = BV(WGM01) /* Clear on Compare match */
107 #if TIMER_PRESCALER == 64
110 #error Unsupported value of TIMER_PRESCALER
113 TCNT0 = 0x00; /* Initialization of Timer/Counter */
114 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
116 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
120 ENABLE_IRQRESTORE(flags);
123 //! Frequency of the hardware high precision timer
124 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
126 INLINE hptime_t timer_hw_hpread(void)
131 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
133 //! Type of time expressed in ticks of the hardware high precision timer
134 typedef uint16_t hptime_t;
136 static void timer_hw_init(void)
139 DISABLE_IRQSAVE(flags);
141 /* Reset Timer overflow flag */
144 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. When changing freq or
145 resolution (top of TCNT), change TIMER_HW_HPTICKS_PER_SEC too */
147 TCCR1A &= ~BV(WGM10);
148 TCCR1B |= BV(WGM12) | BV(CS10);
149 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
151 TCNT1 = 0x00; /* initialization of Timer/Counter */
153 /* Enable timer interrupt: Timer/Counter1 Overflow */
156 ENABLE_IRQRESTORE(flags);
159 //! Frequency of the hardware high precision timer
160 #define TIMER_HW_HPTICKS_PER_SEC (24000ul * 512)
162 INLINE hptime_t timer_hw_hpread(void)
167 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
169 //! Type of time expressed in ticks of the hardware high precision timer
170 typedef uint8_t hptime_t;
172 static void timer_hw_init(void)
175 DISABLE_IRQSAVE(flags);
177 /* Reset Timer flags */
178 TIFR = BV(OCF2) | BV(TOV2);
180 /* Setup Timer/Counter interrupt */
182 #if TIMER_PRESCALER == 64
183 | BV(CS21) | BV(CS20)
185 #error Unsupported value of TIMER_PRESCALER
188 /* Clear on Compare match & prescaler = 64, internal sys clock.
189 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
190 TCNT2 = 0x00; /* initialization of Timer/Counter */
191 OCR2 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
193 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
197 ENABLE_IRQRESTORE(flags);
200 //! Frequency of the hardware high precision timer
201 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
203 INLINE hptime_t timer_hw_hpread(void)
209 #error Unimplemented value for CONFIG_TIMER
210 #endif /* CONFIG_TIMER */
213 #if (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
215 #define DEFINE_TIMER_ISR \
216 static void timer_handler(void)
221 * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
222 * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
223 * handler is really a counter that call the true handler in timer.c
226 SIGNAL(SIG_OVERFLOW1)
228 #if (ARCH & ARCH_BOARD_KC)
230 * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
231 * of conversion (auto-triggered with timer 1 overflow).
232 * The switch can be done 2 ADC cycles after start of conversion.
233 * The handler prologue takes a little more than 32 CPU cycles: with
234 * the prescaler at 1/16 the timing should be correct even at the start
237 * The switch is synchronized with the ADC handler using _adc_trigger_lock.
239 * Mel (A Real Programmer)
241 extern uint8_t _adc_idx_next;
242 extern bool _adc_trigger_lock;
244 if (!_adc_trigger_lock)
247 * Disable free-running mode to avoid starting a
248 * new conversion before the ADC handler has read
249 * the ongoing one. This condition could occur
250 * under very high interrupt load and would have the
251 * unwanted effect of reading from the wrong ADC
254 * NOTE: writing 0 to ADSC and ADIF has no effect.
256 ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
258 ADC_SETCHN(_adc_idx_next);
259 _adc_trigger_lock = true;
261 #endif // ARCH_BOARD_KC
264 * How many timer overflows we must count before calling the real
266 * When the timer is programmed to overflow at 24 kHz, a value of
267 * 24 will result in 1ms between each call.
269 #define TIMER1_OVF_COUNT 24
270 //#warning TIMER1_OVF_COUNT for timer at 12 kHz
271 //#define TIMER1_OVF_COUNT 12
273 static uint8_t count = TIMER1_OVF_COUNT;
279 count = TIMER1_OVF_COUNT;
283 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
285 #define DEFINE_TIMER_ISR \
286 SIGNAL(SIG_OUTPUT_COMPARE0)
288 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
290 #define DEFINE_TIMER_ISR \
291 SIGNAL(SIG_OUTPUT_COMPARE2)
294 #error Unimplemented value for CONFIG_TIMER
295 #endif /* CONFIG_TIMER */
297 #endif /* DRV_TIMER_AVR_H */