4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@develer.com>
6 * This file is part of DevLib - See devlib/README for information.
11 * \author Bernardo Innocenti <bernie@develer.com>
13 * \brief Low-level timer module for AVR
18 *#* Revision 1.21 2004/12/13 12:07:06 bernie
19 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
21 *#* Revision 1.20 2004/11/16 20:59:46 bernie
22 *#* Include <avr/io.h> explicitly.
24 *#* Revision 1.19 2004/10/19 08:56:41 bernie
25 *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong.
27 *#* Revision 1.18 2004/09/20 03:31:03 bernie
28 *#* Fix racy racy code.
30 *#* Revision 1.17 2004/09/14 21:07:09 bernie
31 *#* Include hw.h explicitly.
33 *#* Revision 1.16 2004/09/06 21:49:26 bernie
34 *#* CONFIG_TIMER_STROBE: be tolerant with missing optional macro.
36 *#* Revision 1.15 2004/08/25 14:12:08 rasky
37 *#* Aggiornato il comment block dei log RCS
39 *#* Revision 1.14 2004/08/24 16:27:01 bernie
40 *#* Add missing headers.
42 *#* Revision 1.13 2004/08/24 14:30:11 bernie
43 *#* Use new-style config macros for drv/timer.c
45 *#* Revision 1.12 2004/08/10 06:59:45 bernie
46 *#* CONFIG_TIMER_STROBE: Define no-op default macros.
48 *#* Revision 1.11 2004/08/03 15:53:17 aleph
51 *#* Revision 1.10 2004/08/02 20:20:29 aleph
52 *#* Merge from project_ks
54 *#* Revision 1.9 2004/07/22 02:01:14 bernie
55 *#* Use TIMER_PRESCALER consistently.
57 #ifndef DRV_TIMER_AVR_H
58 #define DRV_TIMER_AVR_H
60 #include <arch_config.h> // ARCH_BOARD_KC
63 #include <avr/signal.h>
66 #if defined(ARCH_BOARD_KC) && (ARCH & ARCH_BOARD_KC)
72 * Values for CONFIG_TIMER.
74 * Select which hardware timer interrupt to use for system clock and softtimers.
75 * \note The timer 1 overflow mode set the timer as a 24 kHz PWM.
77 #define TIMER_ON_OUTPUT_COMPARE0 1
78 #define TIMER_ON_OVERFLOW1 2
79 #define TIMER_ON_OUTPUT_COMPARE2 3
82 /* Not needed, IRQ timer flag cleared automatically */
83 #define timer_hw_irq() do {} while (0)
85 #define TIMER_PRESCALER 64
88 * System timer: additional division after the prescaler
89 * 12288000 / 64 / 192 (0..191) = 1 ms
91 #define OCR_DIVISOR (CLOCK_FREQ / TIMER_PRESCALER / TICKS_PER_SEC - 1) /* 191 */
93 /*! HW dependent timer initialization */
94 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
96 //! Type of time expressed in ticks of the hardware high-precision timer
97 typedef uint8_t hptime_t;
99 static void timer_hw_init(void)
102 IRQ_SAVE_DISABLE(flags);
104 /* Reset Timer flags */
105 TIFR = BV(OCF0) | BV(TOV0);
107 /* Setup Timer/Counter interrupt */
108 ASSR = 0x00; /* Internal system clock */
109 TCCR0 = BV(WGM01) /* Clear on Compare match */
110 #if TIMER_PRESCALER == 64
113 #error Unsupported value of TIMER_PRESCALER
116 TCNT0 = 0x00; /* Initialization of Timer/Counter */
117 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
119 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
126 //! Frequency of the hardware high precision timer
127 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
129 INLINE hptime_t timer_hw_hpread(void)
134 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
136 //! Type of time expressed in ticks of the hardware high precision timer
137 typedef uint16_t hptime_t;
139 static void timer_hw_init(void)
142 IRQ_SAVE_DISABLE(flags);
144 /* Reset Timer overflow flag */
147 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. When changing freq or
148 resolution (top of TCNT), change TIMER_HW_HPTICKS_PER_SEC too */
150 TCCR1A &= ~BV(WGM10);
151 TCCR1B |= BV(WGM12) | BV(CS10);
152 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
154 TCNT1 = 0x00; /* initialization of Timer/Counter */
156 /* Enable timer interrupt: Timer/Counter1 Overflow */
162 //! Frequency of the hardware high precision timer
163 #define TIMER_HW_HPTICKS_PER_SEC (24000ul * 512)
165 INLINE hptime_t timer_hw_hpread(void)
170 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
172 //! Type of time expressed in ticks of the hardware high precision timer
173 typedef uint8_t hptime_t;
175 static void timer_hw_init(void)
178 IRQ_SAVE_DISABLE(flags);
180 /* Reset Timer flags */
181 TIFR = BV(OCF2) | BV(TOV2);
183 /* Setup Timer/Counter interrupt */
185 #if TIMER_PRESCALER == 64
186 | BV(CS21) | BV(CS20)
188 #error Unsupported value of TIMER_PRESCALER
191 /* Clear on Compare match & prescaler = 64, internal sys clock.
192 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
193 TCNT2 = 0x00; /* initialization of Timer/Counter */
194 OCR2 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
196 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
203 //! Frequency of the hardware high precision timer
204 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
206 INLINE hptime_t timer_hw_hpread(void)
212 #error Unimplemented value for CONFIG_TIMER
213 #endif /* CONFIG_TIMER */
216 #if (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
218 #define DEFINE_TIMER_ISR \
219 static void timer_handler(void)
224 * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
225 * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
226 * handler is really a counter that call the true handler in timer.c
229 SIGNAL(SIG_OVERFLOW1)
231 #if (ARCH & ARCH_BOARD_KC)
233 * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
234 * of conversion (auto-triggered with timer 1 overflow).
235 * The switch can be done 2 ADC cycles after start of conversion.
236 * The handler prologue takes a little more than 32 CPU cycles: with
237 * the prescaler at 1/16 the timing should be correct even at the start
240 * The switch is synchronized with the ADC handler using _adc_trigger_lock.
242 * Mel (A Real Programmer)
244 extern uint8_t _adc_idx_next;
245 extern bool _adc_trigger_lock;
247 if (!_adc_trigger_lock)
250 * Disable free-running mode to avoid starting a
251 * new conversion before the ADC handler has read
252 * the ongoing one. This condition could occur
253 * under very high interrupt load and would have the
254 * unwanted effect of reading from the wrong ADC
257 * NOTE: writing 0 to ADSC and ADIF has no effect.
259 ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
261 ADC_SETCHN(_adc_idx_next);
262 _adc_trigger_lock = true;
264 #endif // ARCH_BOARD_KC
267 * How many timer overflows we must count before calling the real
269 * When the timer is programmed to overflow at 24 kHz, a value of
270 * 24 will result in 1ms between each call.
272 #define TIMER1_OVF_COUNT 24
273 //#warning TIMER1_OVF_COUNT for timer at 12 kHz
274 //#define TIMER1_OVF_COUNT 12
276 static uint8_t count = TIMER1_OVF_COUNT;
282 count = TIMER1_OVF_COUNT;
286 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
288 #define DEFINE_TIMER_ISR \
289 SIGNAL(SIG_OUTPUT_COMPARE0)
291 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
293 #define DEFINE_TIMER_ISR \
294 SIGNAL(SIG_OUTPUT_COMPARE2)
297 #error Unimplemented value for CONFIG_TIMER
298 #endif /* CONFIG_TIMER */
300 #endif /* DRV_TIMER_AVR_H */