4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@develer.com>
6 * This file is part of DevLib - See devlib/README for information.
11 * \author Bernardo Innocenti <bernie@develer.com>
13 * \brief Low-level timer module for AVR
18 *#* Revision 1.22 2005/01/23 12:26:07 bernie
19 *#* Add missing header.
21 *#* Revision 1.21 2004/12/13 12:07:06 bernie
22 *#* DISABLE_IRQSAVE/ENABLE_IRQRESTORE: Convert to IRQ_SAVE_DISABLE/IRQ_RESTORE.
24 *#* Revision 1.20 2004/11/16 20:59:46 bernie
25 *#* Include <avr/io.h> explicitly.
27 *#* Revision 1.19 2004/10/19 08:56:41 bernie
28 *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong.
30 *#* Revision 1.18 2004/09/20 03:31:03 bernie
31 *#* Fix racy racy code.
33 *#* Revision 1.17 2004/09/14 21:07:09 bernie
34 *#* Include hw.h explicitly.
36 *#* Revision 1.16 2004/09/06 21:49:26 bernie
37 *#* CONFIG_TIMER_STROBE: be tolerant with missing optional macro.
39 *#* Revision 1.15 2004/08/25 14:12:08 rasky
40 *#* Aggiornato il comment block dei log RCS
42 *#* Revision 1.14 2004/08/24 16:27:01 bernie
43 *#* Add missing headers.
45 *#* Revision 1.13 2004/08/24 14:30:11 bernie
46 *#* Use new-style config macros for drv/timer.c
48 *#* Revision 1.12 2004/08/10 06:59:45 bernie
49 *#* CONFIG_TIMER_STROBE: Define no-op default macros.
51 *#* Revision 1.11 2004/08/03 15:53:17 aleph
54 *#* Revision 1.10 2004/08/02 20:20:29 aleph
55 *#* Merge from project_ks
57 *#* Revision 1.9 2004/07/22 02:01:14 bernie
58 *#* Use TIMER_PRESCALER consistently.
60 #ifndef DRV_TIMER_AVR_H
61 #define DRV_TIMER_AVR_H
63 #include <arch_config.h> // ARCH_BOARD_KC
64 #include <macros.h> // BV()
67 #include <avr/signal.h>
70 #if defined(ARCH_BOARD_KC) && (ARCH & ARCH_BOARD_KC)
76 * Values for CONFIG_TIMER.
78 * Select which hardware timer interrupt to use for system clock and softtimers.
79 * \note The timer 1 overflow mode set the timer as a 24 kHz PWM.
81 #define TIMER_ON_OUTPUT_COMPARE0 1
82 #define TIMER_ON_OVERFLOW1 2
83 #define TIMER_ON_OUTPUT_COMPARE2 3
86 /* Not needed, IRQ timer flag cleared automatically */
87 #define timer_hw_irq() do {} while (0)
89 #define TIMER_PRESCALER 64
92 * System timer: additional division after the prescaler
93 * 12288000 / 64 / 192 (0..191) = 1 ms
95 #define OCR_DIVISOR (CLOCK_FREQ / TIMER_PRESCALER / TICKS_PER_SEC - 1) /* 191 */
97 /*! HW dependent timer initialization */
98 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
100 //! Type of time expressed in ticks of the hardware high-precision timer
101 typedef uint8_t hptime_t;
103 static void timer_hw_init(void)
106 IRQ_SAVE_DISABLE(flags);
108 /* Reset Timer flags */
109 TIFR = BV(OCF0) | BV(TOV0);
111 /* Setup Timer/Counter interrupt */
112 ASSR = 0x00; /* Internal system clock */
113 TCCR0 = BV(WGM01) /* Clear on Compare match */
114 #if TIMER_PRESCALER == 64
117 #error Unsupported value of TIMER_PRESCALER
120 TCNT0 = 0x00; /* Initialization of Timer/Counter */
121 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
123 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
130 //! Frequency of the hardware high precision timer
131 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
133 INLINE hptime_t timer_hw_hpread(void)
138 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
140 //! Type of time expressed in ticks of the hardware high precision timer
141 typedef uint16_t hptime_t;
143 static void timer_hw_init(void)
146 IRQ_SAVE_DISABLE(flags);
148 /* Reset Timer overflow flag */
151 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. When changing freq or
152 resolution (top of TCNT), change TIMER_HW_HPTICKS_PER_SEC too */
154 TCCR1A &= ~BV(WGM10);
155 TCCR1B |= BV(WGM12) | BV(CS10);
156 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
158 TCNT1 = 0x00; /* initialization of Timer/Counter */
160 /* Enable timer interrupt: Timer/Counter1 Overflow */
166 //! Frequency of the hardware high precision timer
167 #define TIMER_HW_HPTICKS_PER_SEC (24000ul * 512)
169 INLINE hptime_t timer_hw_hpread(void)
174 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
176 //! Type of time expressed in ticks of the hardware high precision timer
177 typedef uint8_t hptime_t;
179 static void timer_hw_init(void)
182 IRQ_SAVE_DISABLE(flags);
184 /* Reset Timer flags */
185 TIFR = BV(OCF2) | BV(TOV2);
187 /* Setup Timer/Counter interrupt */
189 #if TIMER_PRESCALER == 64
190 | BV(CS21) | BV(CS20)
192 #error Unsupported value of TIMER_PRESCALER
195 /* Clear on Compare match & prescaler = 64, internal sys clock.
196 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
197 TCNT2 = 0x00; /* initialization of Timer/Counter */
198 OCR2 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
200 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
207 //! Frequency of the hardware high precision timer
208 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
210 INLINE hptime_t timer_hw_hpread(void)
216 #error Unimplemented value for CONFIG_TIMER
217 #endif /* CONFIG_TIMER */
220 #if (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
222 #define DEFINE_TIMER_ISR \
223 static void timer_handler(void)
228 * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
229 * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
230 * handler is really a counter that call the true handler in timer.c
233 SIGNAL(SIG_OVERFLOW1)
235 #if (ARCH & ARCH_BOARD_KC)
237 * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
238 * of conversion (auto-triggered with timer 1 overflow).
239 * The switch can be done 2 ADC cycles after start of conversion.
240 * The handler prologue takes a little more than 32 CPU cycles: with
241 * the prescaler at 1/16 the timing should be correct even at the start
244 * The switch is synchronized with the ADC handler using _adc_trigger_lock.
246 * Mel (A Real Programmer)
248 extern uint8_t _adc_idx_next;
249 extern bool _adc_trigger_lock;
251 if (!_adc_trigger_lock)
254 * Disable free-running mode to avoid starting a
255 * new conversion before the ADC handler has read
256 * the ongoing one. This condition could occur
257 * under very high interrupt load and would have the
258 * unwanted effect of reading from the wrong ADC
261 * NOTE: writing 0 to ADSC and ADIF has no effect.
263 ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
265 ADC_SETCHN(_adc_idx_next);
266 _adc_trigger_lock = true;
268 #endif // ARCH_BOARD_KC
271 * How many timer overflows we must count before calling the real
273 * When the timer is programmed to overflow at 24 kHz, a value of
274 * 24 will result in 1ms between each call.
276 #define TIMER1_OVF_COUNT 24
277 //#warning TIMER1_OVF_COUNT for timer at 12 kHz
278 //#define TIMER1_OVF_COUNT 12
280 static uint8_t count = TIMER1_OVF_COUNT;
286 count = TIMER1_OVF_COUNT;
290 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
292 #define DEFINE_TIMER_ISR \
293 SIGNAL(SIG_OUTPUT_COMPARE0)
295 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
297 #define DEFINE_TIMER_ISR \
298 SIGNAL(SIG_OUTPUT_COMPARE2)
301 #error Unimplemented value for CONFIG_TIMER
302 #endif /* CONFIG_TIMER */
304 #endif /* DRV_TIMER_AVR_H */