4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@develer.com>
6 * This file is part of DevLib - See devlib/README for information.
11 * \author Bernardo Innocenti <bernie@develer.com>
13 * \brief Low-level timer module for AVR
18 *#* Revision 1.18 2004/09/20 03:31:03 bernie
19 *#* Fix racy racy code.
21 *#* Revision 1.17 2004/09/14 21:07:09 bernie
22 *#* Include hw.h explicitly.
24 *#* Revision 1.16 2004/09/06 21:49:26 bernie
25 *#* CONFIG_TIMER_STROBE: be tolerant with missing optional macro.
27 *#* Revision 1.15 2004/08/25 14:12:08 rasky
28 *#* Aggiornato il comment block dei log RCS
30 *#* Revision 1.14 2004/08/24 16:27:01 bernie
31 *#* Add missing headers.
33 *#* Revision 1.13 2004/08/24 14:30:11 bernie
34 *#* Use new-style config macros for drv/timer.c
36 *#* Revision 1.12 2004/08/10 06:59:45 bernie
37 *#* CONFIG_TIMER_STROBE: Define no-op default macros.
39 *#* Revision 1.11 2004/08/03 15:53:17 aleph
42 *#* Revision 1.10 2004/08/02 20:20:29 aleph
43 *#* Merge from project_ks
45 *#* Revision 1.9 2004/07/22 02:01:14 bernie
46 *#* Use TIMER_PRESCALER consistently.
48 #ifndef DRV_TIMER_AVR_H
49 #define DRV_TIMER_AVR_H
51 #include <arch_config.h> // ARCH_BOARD_KC
55 #include <avr/signal.h>
57 #if defined(ARCH_BOARD_KC) && (ARCH & ARCH_BOARD_KC)
63 * Values for CONFIG_TIMER.
65 * Select which hardware timer interrupt to use for system clock and softtimers.
66 * \note The timer 1 overflow mode set the timer as a 24 kHz PWM.
68 #define TIMER_ON_OUTPUT_COMPARE0 1
69 #define TIMER_ON_OVERFLOW1 2
70 #define TIMER_ON_OUTPUT_COMPARE2 3
74 * \def CONFIG_TIMER_STROBE
76 * This is a debug facility that can be used to
77 * monitor timer interrupt activity on an external pin.
79 * To use strobes, redefine the macros TIMER_STROBE_ON,
80 * TIMER_STROBE_OFF and TIMER_STROBE_INIT and set
81 * CONFIG_TIMER_STROBE to 1.
83 #if !defined(CONFIG_TIMER_STROBE) || !CONFIG_TIMER_STROBE
84 #define TIMER_STROBE_ON do {/*nop*/} while(0)
85 #define TIMER_STROBE_OFF do {/*nop*/} while(0)
86 #define TIMER_STROBE_INIT do {/*nop*/} while(0)
90 /* Not needed, IRQ timer flag cleared automatically */
91 #define timer_hw_irq() do {} while (0)
93 #define TIMER_PRESCALER 64
96 * System timer: additional division after the prescaler
97 * 12288000 / 64 / 192 (0..191) = 1 ms
99 #define OCR_DIVISOR (CLOCK_FREQ / TIMER_PRESCALER / TICKS_PER_SEC - 1) /* 191 */
101 /*! HW dependent timer initialization */
102 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
104 //! Type of time expressed in ticks of the hardware high-precision timer
105 typedef uint8_t hptime_t;
107 static void timer_hw_init(void)
110 DISABLE_IRQSAVE(flags);
112 /* Reset Timer flags */
113 TIFR = BV(OCF0) | BV(TOV0);
115 /* Setup Timer/Counter interrupt */
116 ASSR = 0x00; /* Internal system clock */
117 TCCR0 = BV(WGM01) /* Clear on Compare match */
118 #if TIMER_PRESCALER == 64
121 #error Unsupported value of TIMER_PRESCALER
124 TCNT0 = 0x00; /* Initialization of Timer/Counter */
125 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
127 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
131 ENABLE_IRQRESTORE(flags);
134 //! Frequency of the hardware high precision timer
135 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
137 INLINE hptime_t timer_hw_hpread(void)
142 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
144 //! Type of time expressed in ticks of the hardware high precision timer
145 typedef uint16_t hptime_t;
147 static void timer_hw_init(void)
150 DISABLE_IRQSAVE(flags);
152 /* Reset Timer overflow flag */
155 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. When changing freq or
156 resolution (top of TCNT), change TIMER_HW_HPTICKS_PER_SEC too */
158 TCCR1A &= ~BV(WGM10);
159 TCCR1B |= BV(WGM12) | BV(CS10);
160 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
162 TCNT1 = 0x00; /* initialization of Timer/Counter */
164 /* Enable timer interrupt: Timer/Counter1 Overflow */
167 ENABLE_IRQRESTORE(flags);
170 //! Frequency of the hardware high precision timer
171 #define TIMER_HW_HPTICKS_PER_SEC (24000ul * 512)
173 INLINE hptime_t timer_hw_hpread(void)
178 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
180 //! Type of time expressed in ticks of the hardware high precision timer
181 typedef uint8_t hptime_t;
183 static void timer_hw_init(void)
186 DISABLE_IRQSAVE(flags);
188 /* Reset Timer flags */
189 TIFR = BV(OCF2) | BV(TOV2);
191 /* Setup Timer/Counter interrupt */
193 #if TIMER_PRESCALER == 64
194 | BV(CS21) | BV(CS20)
196 #error Unsupported value of TIMER_PRESCALER
199 /* Clear on Compare match & prescaler = 64, internal sys clock.
200 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
201 TCNT2 = 0x00; /* initialization of Timer/Counter */
202 OCR2 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
204 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
208 ENABLE_IRQRESTORE(flags);
211 //! Frequency of the hardware high precision timer
212 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
214 INLINE hptime_t timer_hw_hpread(void)
220 #error Unimplemented value for CONFIG_TIMER
221 #endif /* CONFIG_TIMER */
224 #if (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
226 #define DEFINE_TIMER_ISR \
227 static void timer_handler(void)
232 * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
233 * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
234 * handler is really a counter that call the true handler in timer.c
237 SIGNAL(SIG_OVERFLOW1)
239 #if (ARCH & ARCH_BOARD_KC)
241 * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
242 * of conversion (auto-triggered with timer 1 overflow).
243 * The switch can be done 2 ADC cycles after start of conversion.
244 * The handler prologue takes a little more than 32 CPU cycles: with
245 * the prescaler at 1/16 the timing should be correct even at the start
248 * The switch is synchronized with the ADC handler using _adc_trigger_lock.
250 * Mel (A Real Programmer)
252 extern uint8_t _adc_idx_next;
253 extern bool _adc_trigger_lock;
255 if (!_adc_trigger_lock)
258 * Disable free-running mode to avoid starting a
259 * new conversion before the ADC handler has read
260 * the ongoing one. This condition could occur
261 * under very high interrupt load and would have the
262 * unwanted effect of reading from the wrong ADC
265 * NOTE: writing 0 to ADSC and ADIF has no effect.
267 ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
269 ADC_SETCHN(_adc_idx_next);
270 _adc_trigger_lock = true;
272 #endif // ARCH_BOARD_KC
275 * How many timer overflows we must count before calling the real
277 * When the timer is programmed to overflow at 24 kHz, a value of
278 * 24 will result in 1ms between each call.
280 #define TIMER1_OVF_COUNT 24
281 //#warning TIMER1_OVF_COUNT for timer at 12 kHz
282 //#define TIMER1_OVF_COUNT 12
284 static uint8_t count = TIMER1_OVF_COUNT;
290 count = TIMER1_OVF_COUNT;
294 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
296 #define DEFINE_TIMER_ISR \
297 SIGNAL(SIG_OUTPUT_COMPARE0)
299 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
301 #define DEFINE_TIMER_ISR \
302 SIGNAL(SIG_OUTPUT_COMPARE2)
305 #error Unimplemented value for CONFIG_TIMER
306 #endif /* CONFIG_TIMER */
308 #endif /* DRV_TIMER_AVR_H */