4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief Configuration file for serial module.
37 * \author Daniele Basile <asterix@develer.com>
44 /// Kdebug console on debug unit
45 #define CONFIG_TRIFACE_PORT 1
47 /// Baud-rate for the kdebug console
48 #define CONFIG_TRIFACE_BAUDRATE 115200
50 /// Triface serial tag port
51 #define TAG_SER_PORT 0
53 ///Baud-rate for triface serial tag port
54 #define TAG_SER_BAUDRATE 9600
56 /// [bytes] Size of the outbound FIFO buffer for port 0.
57 #define CONFIG_UART0_TXBUFSIZE 32
59 /// [bytes] Size of the inbound FIFO buffer for port 0.
60 #define CONFIG_UART0_RXBUFSIZE 64
62 /// [bytes] Size of the outbound FIFO buffer for port 1.
63 #define CONFIG_UART1_TXBUFSIZE 32
65 /// [bytes] Size of the inbound FIFO buffer for port 1.
66 #define CONFIG_UART1_RXBUFSIZE 64
69 /// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
70 #define CONFIG_SPI_TXBUFSIZE 32
72 /// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
73 #define CONFIG_SPI_RXBUFSIZE 32
75 /// [bytes] Size of the outbound FIFO buffer for SPI port 0.
76 #define CONFIG_SPI0_TXBUFSIZE 32
78 /// [bytes] Size of the inbound FIFO buffer for SPI port 0.
79 #define CONFIG_SPI0_RXBUFSIZE 32
81 /// [bytes] Size of the outbound FIFO buffer for SPI port 1.
82 #define CONFIG_SPI1_TXBUFSIZE 32
84 /// [bytes] Size of the inbound FIFO buffer for SPI port 1.
85 #define CONFIG_SPI1_RXBUFSIZE 32
87 /// SPI data order (AVR only).
88 #define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST
90 /// SPI clock division factor (AVR only).
91 #define CONFIG_SPI_CLOCK_DIV 16
93 /// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
94 #define CONFIG_SPI_CLOCK_POL 0
96 /// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
97 #define CONFIG_SPI_CLOCK_PHASE 0
99 /// Default transmit timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
100 #define CONFIG_SER_TXTIMEOUT 0
102 /// Default receive timeout (ms). Set to -1 for infinite timeout, 0 for null timeout
103 #define CONFIG_SER_RXTIMEOUT 0
105 /// Use RTS/CTS handshake
106 #define CONFIG_SER_HWHANDSHAKE 0
108 /// Default baud rate (set to 0 to disable).
109 #define CONFIG_SER_DEFBAUDRATE 0
111 /// For serial debug.
112 #define CONFIG_SER_STROBE 0
114 #endif /* CFG_SER_H */