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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "hsmci_sam3.h"
41 #include <drv/timer.h>
42 #include <drv/irq_cm3.h>
43 #include <drv/dmac_sam3.h>
50 #define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1)
53 #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
54 | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
56 #define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE))
58 #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
62 } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
65 #define HSMCI_WAIT_DATA_RDY()\
68 } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
71 #define HSMCI_DMAC_CH 0
73 static DECLARE_ISR(hsmci_irq)
75 uint32_t status = HSMCI_SR;
76 if (status & BV(HSMCI_IER_DMADONE))
82 void hsmci_readResp(uint32_t *resp, size_t len)
86 for (size_t i = 0; i < len ; i++)
90 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
94 HSMCI_ARGR = argument;
95 HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);
97 uint32_t status = HSMCI_SR;
98 while (!(status & BV(HSMCI_SR_CMDRDY)))
100 if (status & HSMCI_RESP_ERROR_MASK)
111 void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size)
113 HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
114 HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
116 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL);
117 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
118 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
119 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
120 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
122 dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR);
123 dmac_configureDmac(HSMCI_DMAC_CH, word_num, cfg, ctrla, ctrlb);
124 dmac_start(HSMCI_DMAC_CH);
127 void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size)
129 HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
130 HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
132 uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL);
133 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
134 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
135 DMAC_CTRLB_FC_PER2MEM_DMA_FC |
136 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
138 dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf);
139 dmac_configureDmac(HSMCI_DMAC_CH, word_num, cfg, ctrla, ctrlb);
140 dmac_start(HSMCI_DMAC_CH);
144 void hsmci_waitTransfer(void)
146 while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
150 void hsmci_setSpeed(uint32_t data_rate, int flag)
152 if (flag & HSMCI_HS_MODE)
153 HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
155 HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
157 HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
162 void hsmci_init(Hsmci *hsmci)
168 pmc_periphEnable(HSMCI_ID);
169 HSMCI_CR = BV(HSMCI_CR_SWRST);
170 HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
171 HSMCI_IDR = 0xFFFFFFFF;
173 HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
174 HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
175 HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
176 HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
178 sysirq_setHandler(INT_HSMCI, hsmci_irq);
179 HSMCI_CR = BV(HSMCI_CR_MCIEN);
182 dmac_enableCh(HSMCI_DMAC_CH, NULL);