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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "hsmci_sam3.h"
41 #include <drv/timer.h>
42 #include <drv/irq_cm3.h>
43 #include <drv/dmac_sam3.h>
45 #include <mware/event.h>
52 #define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1)
55 #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
56 | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
58 #define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE))
60 #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
64 } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
67 #define HSMCI_WAIT_DATA_RDY()\
70 } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
73 #define HSMCI_DMAC_CH 3
76 void hsmci_readResp(uint32_t *resp, size_t len)
80 for (size_t i = 0; i < len ; i++)
84 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
88 HSMCI_ARGR = argument;
89 HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);
95 if (status & HSMCI_RESP_ERROR_MASK)
100 } while (!(status & BV(HSMCI_SR_CMDRDY)));
105 #define HSMCI_WRITE_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \
107 ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
108 (0 & DMAC_CFG_SRC_PER_MASK))
110 #define HSMCI_WRITE_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
111 DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
112 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING)
114 #define HSMCI_WRITE_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
115 DMAC_CTRLA_DST_WIDTH_WORD)
117 #define HSMCI_READ_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
119 ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
120 (0 & DMAC_CFG_SRC_PER_MASK))
122 #define HSMCI_READ_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
123 DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
124 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED)
126 #define HSMCI_READ_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
127 DMAC_CTRLA_DST_WIDTH_WORD)
130 void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size)
132 HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
133 HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT) & ~0x30000;
135 dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR);
136 dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_WRITE_DMAC_CFG, HSMCI_WRITE_DMAC_CTRLA, HSMCI_WRITE_DMAC_CTRLB);
137 dmac_start(HSMCI_DMAC_CH);
140 void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size)
142 HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
143 HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
145 dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf);
146 dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_READ_DMAC_CFG, HSMCI_READ_DMAC_CTRLA, HSMCI_READ_DMAC_CTRLB);
147 dmac_start(HSMCI_DMAC_CH);
151 void hsmci_waitTransfer(void)
153 while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
157 void hsmci_setSpeed(uint32_t data_rate, int flag)
159 if (flag & HSMCI_HS_MODE)
160 HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
162 HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
164 HSMCI_MR = HSMCI_CLK_DIV(data_rate);
169 void hsmci_init(Hsmci *hsmci)
175 pmc_periphEnable(HSMCI_ID);
176 HSMCI_CR = BV(HSMCI_CR_SWRST);
177 HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
178 HSMCI_IDR = 0xFFFFFFFF;
180 HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
181 HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
182 HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED);
183 HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
185 HSMCI_CR = BV(HSMCI_CR_MCIEN);
188 dmac_enableCh(HSMCI_DMAC_CH, NULL);