4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Cortex-M3 architecture's entry point
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cfg/debug.h>
41 #include "drv/clock.h"
44 extern size_t _etext, __data_start, __data_end,
45 __bss_start, __bss_end, __stack_irq_end;
47 extern int main(void);
49 /* Architecture's entry point */
50 static void NORETURN _entry(void)
55 * PLL may not function properly at default LDO setting.
59 * In designs that enable and use the PLL module, unstable device
60 * behavior may occur with the LDO set at its default of 2.5 volts or
61 * below (minimum of 2.25 volts). Designs that do not use the PLL
62 * module are not affected.
64 * Workaround: Prior to enabling the PLL module, it is recommended that
65 * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
66 * the LDO Power Control (LDOPCTL) register.
68 * Silicon Revision Affected: A1, A2
70 * See also: Stellaris LM3S1968 A2 Errata documentation.
72 if (REVISION_IS_A1 | REVISION_IS_A2)
73 HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
75 /* Set the appropriate clocking configuration */
78 /* Copy the data segment initializers from flash to SRAM */
80 for (dst = &__data_start; dst < &__data_end ; )
83 /* Zero fill the bss segment */
84 for (dst = &__bss_start; dst < &__bss_end ; )
87 /* Initialize IRQ vector table in RAM */
90 /* Call the application's entry point */
95 static void nmi_isr(void)
100 static void fault_isr(void)
105 static void default_isr(void)
110 /* Startup vector table */
111 static void (* const irq_vectors[])(void) __attribute__ ((section(".vectors"))) = {
112 (void (*)(void))&__stack_irq_end, /* Initial stack pointer */
113 _entry, /* The reset handler */
114 nmi_isr, /* The NMI handler */
115 fault_isr, /* The hard fault handler */
116 default_isr, /* The MPU fault handler */
117 default_isr, /* The bus fault handler */
118 default_isr, /* The usage fault handler */
123 default_isr, /* SVCall handler */
124 default_isr, /* Debug monitor handler */
126 default_isr, /* The PendSV handler */
127 default_isr, /* The SysTick handler */
128 default_isr, /* GPIO Port A */
129 default_isr, /* GPIO Port B */
130 default_isr, /* GPIO Port C */
131 default_isr, /* GPIO Port D */
132 default_isr, /* GPIO Port E */
133 default_isr, /* UART0 Rx and Tx */
134 default_isr, /* UART1 Rx and Tx */
135 default_isr, /* SSI0 Rx and Tx */
136 default_isr, /* I2C0 Master and Slave */
137 default_isr, /* PWM Fault */
138 default_isr, /* PWM Generator 0 */
139 default_isr, /* PWM Generator 1 */
140 default_isr, /* PWM Generator 2 */
141 default_isr, /* Quadrature Encoder 0 */
142 default_isr, /* ADC Sequence 0 */
143 default_isr, /* ADC Sequence 1 */
144 default_isr, /* ADC Sequence 2 */
145 default_isr, /* ADC Sequence 3 */
146 default_isr, /* Watchdog timer */
147 default_isr, /* Timer 0 subtimer A */
148 default_isr, /* Timer 0 subtimer B */
149 default_isr, /* Timer 1 subtimer A */
150 default_isr, /* Timer 1 subtimer B */
151 default_isr, /* Timer 2 subtimer A */
152 default_isr, /* Timer 2 subtimer B */
153 default_isr, /* Analog Comparator 0 */
154 default_isr, /* Analog Comparator 1 */
155 default_isr, /* Analog Comparator 2 */
156 default_isr, /* System Control (PLL, OSC, BO) */
157 default_isr, /* FLASH Control */
158 default_isr, /* GPIO Port F */
159 default_isr, /* GPIO Port G */
160 default_isr, /* GPIO Port H */
161 default_isr, /* UART2 Rx and Tx */
162 default_isr, /* SSI1 Rx and Tx */
163 default_isr, /* Timer 3 subtimer A */
164 default_isr, /* Timer 3 subtimer B */
165 default_isr, /* I2C1 Master and Slave */
166 default_isr, /* Quadrature Encoder 1 */
167 default_isr, /* CAN0 */
168 default_isr, /* CAN1 */
169 default_isr, /* CAN2 */
170 default_isr, /* Ethernet */
171 default_isr /* Hibernate */