4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the LM3S I2C (implementation)
37 #include "cfg/cfg_i2c.h"
39 #define LOG_LEVEL I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/detect.h>
51 #include <io/cm3_types.h>
54 #include <drv/timer.h>
56 #include <drv/gpio_lm3s.h>
57 #include <drv/clock_lm3s.h>
64 #define I2C I2C0_MASTER_BASE
65 #define SYSCTL_RCGC1_I2C SYSCTL_RCGC1_I2C0
66 #define SYSCTL_RCGC2_GPIO SYSCTL_RCGC2_GPIOB
67 #define GPIO_I2C_SCL_PIN GPIO_I2C0_SCL_PIN
68 #define GPIO_I2C_SDA_PIN GPIO_I2C0_SDA_PIN
69 #define GPIO_PORT_BASE GPIO_PORTB_BASE
72 #define I2C I2C1_MASTER_BASE
73 #define SYSCTL_RCGC1_I2C SYSCTL_RCGC1_I2C1
74 #define SYSCTL_RCGC2_GPIO SYSCTL_RCGC2_GPIOA
75 #define GPIO_I2C_SCL_PIN GPIO_I2C1_SCL_PIN
76 #define GPIO_I2C_SDA_PIN GPIO_I2C1_SDA_PIN
77 #define GPIO_PORT_BASE GPIO_PORTA_BASE
82 * Send START condition and select slave for write.
83 * \c id is the device id comprehensive of address left shifted by 1.
84 * The LSB of \c id is ignored and reset to 0 for write operation.
86 * \return true on success, false otherwise.
88 bool i2c_builtin_start_w(uint8_t id)
90 HWREG(I2C + I2C_O_MSA) = id & ~BV(0);
96 * Send START condition and select slave for read.
97 * \c id is the device id comprehensive of address left shifted by 1.
98 * The LSB of \c id is ignored and set to 1 for read operation.
100 * \return true on success, false otherwise.
102 bool i2c_builtin_start_r(uint8_t id)
104 HWREG(I2C + I2C_O_MSA) = id | 1;
109 void i2c_builtin_stop(void)
114 bool i2c_builtin_put(const uint8_t data)
121 int i2c_builtin_get(bool ack)
127 INLINE bool check_ack(uint32_t mode_mask)
129 ticks_t start = timer_clock();
130 while ( HWREG(I2C + I2C_O_MCS) & I2C_MCS_ADRACK )
132 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
134 LOG_ERR("Timeout on I2C_START\n");
138 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_ERROR_STOP;
140 HWREG(I2C + I2C_O_MCS) = mode_mask;
141 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
149 * With this function is allowed only the atomic write.
151 bool i2c_send(const void *_buf, size_t count)
153 const uint8_t *buf = (const uint8_t *)_buf;
157 HWREGB(I2C + I2C_O_MDR) = *buf;
159 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_SEND;
161 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
163 if ( !check_ack(I2C_MASTER_CMD_SINGLE_SEND) )
172 HWREGB(I2C + I2C_O_MDR) = *buf++;
175 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_START;
177 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
179 if ( !check_ack(I2C_MASTER_CMD_BURST_SEND_START) )
184 HWREGB(I2C + I2C_O_MDR) = *buf++;
186 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_CONT;
187 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
191 HWREGB(I2C + I2C_O_MDR) = *buf++;
193 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_FINISH;
194 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
201 * In order to read bytes from the i2c we should make some tricks.
203 bool i2c_recv(void *_buf, size_t count)
205 uint8_t *buf = (uint8_t *)_buf;
209 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_RECEIVE;
210 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
212 if ( !check_ack(I2C_MASTER_CMD_SINGLE_RECEIVE) )
215 *buf++ = HWREG(I2C + I2C_O_MDR);
222 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_START;
223 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
225 if ( !check_ack(I2C_MASTER_CMD_BURST_RECEIVE_START) )
228 *buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
234 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_CONT;
235 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
236 *buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
240 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_FINISH;
241 while( HWREG(I2C + I2C_O_MCS) & I2C_MCS_BUSY );
243 *buf++ = (uint8_t)HWREG(I2C + I2C_O_MDR);
253 * Initialize I2C module.
255 void i2c_builtin_init(void)
258 /* Enable the peripheral clock */
259 SYSCTL_RCGC1_R |= SYSCTL_RCGC1_I2C;
260 SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIO;
262 /* Configure GPIO pins to work as I2C pins */
263 lm3s_gpioPinConfig(GPIO_PORT_BASE, GPIO_I2C_SCL_PIN,
264 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
266 lm3s_gpioPinConfig(GPIO_PORT_BASE, GPIO_I2C_SDA_PIN,
267 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
270 * Compute the clock divider that achieves the fastest speed less than or
271 * equal to the desired speed. The numerator is biased to favor a larger
272 * clock divider so that the resulting clock is always less than or equal
273 * to the desired clock, never greater.
275 HWREG(I2C + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * CONFIG_I2C_FREQ) - 1) / (2 * 10 * CONFIG_I2C_FREQ)) - 1;
278 //Enable I2C in master mode
279 HWREG(I2C + I2C_O_MCR) |= I2C_MCR_MFE;