4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx I2C driver.
35 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2c.h"
40 #define LOG_LEVEL I2C_LOG_LEVEL
41 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <drv/gpio_stm32.h>
49 #include <drv/irq_cm3.h>
50 #include <drv/clock_stm32.h>
55 struct stm32_i2c *i2c = (struct stm32_i2c *)I2C1_BASE;
57 INLINE uint32_t get_status(struct stm32_i2c *base)
59 return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
63 * Send START condition on the bus.
65 * \return true on success, false otherwise.
67 static bool i2c_builtin_start(void)
69 i2c->CR1 |= CR1_ACK_SET;
70 i2c->CR1 |= CR1_PE_SET;
71 i2c->CR1 |= CR1_START_SET;
73 while (get_status(i2c) != I2C_EVENT_MASTER_MODE_SELECT);
80 * Send START condition and select slave for write.
81 * \c id is the device id comprehensive of address left shifted by 1.
82 * The LSB of \c id is ignored and reset to 0 for write operation.
84 * \return true on success, false otherwise.
86 bool i2c_builtin_start_w(uint8_t id)
88 id &= OAR1_ADD0_RESET;
93 while (get_status(i2c) != I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED);
100 * Send START condition and select slave for read.
101 * \c id is the device id comprehensive of address left shifted by 1.
102 * The LSB of \c id is ignored and set to 1 for read operation.
104 * \return true on success, false otherwise.
106 bool i2c_builtin_start_r(uint8_t id)
113 while (get_status(i2c) != I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED);
120 * Send STOP condition.
122 void i2c_builtin_stop(void)
124 i2c->CR1 |= CR1_STOP_SET;
125 i2c->CR1 &= CR1_PE_RESET;
130 * Put a single byte in master transmitter mode
131 * to the selected slave device through the TWI bus.
133 * \return true on success, false on error.
135 bool i2c_builtin_put(const uint8_t data)
138 while (get_status(i2c) != I2C_EVENT_MASTER_BYTE_TRANSMITTED);
144 * Get 1 byte from slave in master transmitter mode
145 * to the selected slave device through the TWI bus.
146 * If \a ack is true issue a ACK after getting the byte,
147 * otherwise a NACK is issued.
149 * \return the byte read if ok, EOF on errors.
151 int i2c_builtin_get(bool ack)
153 while (get_status(i2c) != I2C_EVENT_MASTER_BYTE_RECEIVED);
162 * Initialize I2C module.
164 void i2c_builtin_init(void)
168 RCC->APB2ENR |= RCC_APB2_GPIOB;
169 RCC->APB1ENR |= RCC_APB1_I2C1;
171 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SCL_PIN,
172 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
174 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SDA_PIN,
175 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
183 i2c->CR2 |= CR2_FREQ_36MHZ;
185 /* Configure spi in standard mode */
186 #if CONFIG_I2C_FREQ <= 100000
187 i2c->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (CONFIG_I2C_FREQ << 1));
188 i2c->TRISE |= (CR2_FREQ_36MHZ + 1);
190 #error fast mode not supported