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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx I2C driver.
35 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2c.h"
40 #define LOG_LEVEL I2C_LOG_LEVEL
41 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <drv/gpio_stm32.h>
49 #include <drv/irq_cm3.h>
50 #include <drv/clock_stm32.h>
52 #include <drv/timer.h>
56 struct stm32_i2c *i2c = (struct stm32_i2c *)I2C1_BASE;
59 #define WAIT_BTF(base) while( !(base->SR1 & BV(SR1_BTF)) )
60 #define WAIT_RXE(base) while( !(base->SR1 & BV(SR1_RXE)) )
62 INLINE uint32_t get_status(struct stm32_i2c *base)
64 return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
68 INLINE bool check_i2cStatus(uint32_t event)
72 uint32_t stat = get_status(i2c);
77 if (stat & SR1_ERR_MASK)
79 LOG_ERR("[%08lx]\n", stat & SR1_ERR_MASK);
80 i2c->SR1 &= ~SR1_ERR_MASK;
82 i2c->CR1 |= CR1_START_SET;
92 * Send START condition on the bus.
94 * \return true on success, false otherwise.
96 static bool i2c_builtin_start(void)
99 i2c->CR1 |= (CR1_ACK_SET | BV(CR1_POS) | CR1_PE_SET);
101 i2c->CR1 |= CR1_START_SET;
103 if(check_i2cStatus(I2C_EVENT_MASTER_MODE_SELECT))
111 * Send START condition and select slave for write.
112 * \c id is the device id comprehensive of address left shifted by 1.
113 * The LSB of \c id is ignored and reset to 0 for write operation.
115 * \return true on success, false otherwise.
117 bool i2c_builtin_start_w(uint8_t id)
121 * Loop on the select write sequence: when the eeprom is busy
122 * writing previously sent data it will reply to the SLA_W
123 * control byte with a NACK. In this case, we must
124 * keep trying until the eeprom responds with an ACK.
126 ticks_t start = timer_clock();
127 while (i2c_builtin_start())
129 i2c->DR = id & OAR1_ADD0_RESET;
131 if(check_i2cStatus(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
134 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
136 LOG_ERR("Timeout on I2C_START\n");
146 * Send START condition and select slave for read.
147 * \c id is the device id comprehensive of address left shifted by 1.
148 * The LSB of \c id is ignored and set to 1 for read operation.
150 * \return true on success, false otherwise.
152 bool i2c_builtin_start_r(uint8_t id)
156 i2c->DR = (id | OAR1_ADD0_SET);
158 if(check_i2cStatus(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
166 * Send STOP condition.
168 void i2c_builtin_stop(void)
170 i2c->CR1 |= CR1_STOP_SET;
171 i2c->CR1 &= CR1_PE_RESET;
176 bool i2c_builtin_put(const uint8_t data)
181 int i2c_builtin_get(bool ack)
187 bool i2c_send(const void *_buf, size_t count)
189 const uint8_t *buf = (const uint8_t *)_buf;
205 if(check_i2cStatus(I2C_EVENT_MASTER_BYTE_TRANSMITTED))
212 * In order to read bytes from the i2c we should make some tricks.
213 * This because the silicon manage automatically the NACK on last byte, so to read
214 * one, two or three byte we should manage separately these cases.
216 bool i2c_recv(void *_buf, size_t count)
218 uint8_t *buf = (uint8_t *)_buf;
224 i2c->CR1 &= ~BV(CR1_POS);
226 if(!check_i2cStatus(I2C_EVENT_MASTER_BYTE_RECEIVED))
229 i2c->CR1 &= CR1_ACK_RESET;
236 i2c->CR1 &= CR1_ACK_RESET;
240 i2c->CR1 |= CR1_STOP_SET;
247 i2c->CR1 &= ~BV(CR1_POS);
252 i2c->CR1 &= ~BV(CR1_POS);
256 i2c->CR1 &= CR1_ACK_RESET;
260 i2c->CR1 |= CR1_STOP_SET;
272 i2c->CR1 &= ~BV(CR1_POS);
288 * Initialize I2C module.
290 void i2c_builtin_init(void)
294 RCC->APB2ENR |= RCC_APB2_GPIOB;
295 RCC->APB1ENR |= RCC_APB1_I2C1;
297 /* Set gpio to use I2C driver */
298 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SCL_PIN,
299 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
301 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SDA_PIN,
302 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
305 /* Clear all needed registers */
312 /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
313 i2c->CR2 |= CR2_FREQ_36MHZ;
315 /* Configure spi in standard mode */
316 #if CONFIG_I2C_FREQ <= 100000
317 i2c->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (CONFIG_I2C_FREQ << 1));
318 i2c->TRISE |= (CR2_FREQ_36MHZ + 1);
320 #error fast mode not supported