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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
39 #include "hw/hw_i2s.h"
41 #include "cfg/cfg_i2s.h"
43 // Define log settings for cfg/log.h.
44 #define LOG_LEVEL I2S_LOG_LEVEL
45 #define LOG_FORMAT I2S_LOG_FORMAT
48 #include <drv/timer.h>
50 #include <drv/dmac_sam3.h>
52 #include <mware/event.h>
63 #define I2S_CACHED_CHUNK_SIZE 2
65 #define I2S_TX_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \
67 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
68 (4 & DMAC_CFG_SRC_PER_MASK))
70 #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
71 DMAC_CTRLA_DST_WIDTH_HALF_WORD)
73 #define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
74 DMAC_CTRLB_DST_INCR_FIXED | \
75 DMAC_CTRLB_SRC_INCR_INCREMENTING)
77 #define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
79 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
80 (4 & DMAC_CFG_SRC_PER_MASK))
82 #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
83 DMAC_CTRLA_DST_WIDTH_HALF_WORD)
85 #define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
86 DMAC_CTRLB_DST_INCR_INCREMENTING | \
87 DMAC_CTRLB_SRC_INCR_FIXED)
95 struct I2sHardware i2s_hw;
96 static Event data_ready;
105 static int16_t *sample_buff;
106 static size_t next_idx = 0;
107 static size_t chunk_size = 0;
108 static size_t remaing_size = 0;
109 static size_t transfer_size = 0;
111 static bool single_transfer;
113 static void sam3_i2s_txStop(I2s *i2s)
116 SSC_CR = BV(SSC_TXDIS);
117 dmac_stop(I2S_DMAC_CH);
124 event_do(&data_ready);
127 static void sam3_i2s_txWait(I2s *i2s)
130 event_wait(&data_ready);
133 static void i2s_dmac_irq(uint32_t status)
138 single_transfer = false;
142 if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
145 // Disable to reset channel and clear fifo
146 dmac_stop(I2S_DMAC_CH);
154 curr->src_addr = (uint32_t)&sample_buff[next_idx];
155 curr->dst_addr = (uint32_t)&SSC_THR;
156 curr->dsc_addr = (uint32_t)next;
157 curr->ctrla = I2S_TX_DMAC_CTRLA | (chunk_size & 0xffff);
158 curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
160 remaing_size -= chunk_size;
161 next_idx += chunk_size;
163 if (remaing_size <= 0)
165 remaing_size = transfer_size;
170 event_do(&data_ready);
175 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
178 ASSERT(len >= slice_len);
179 ASSERT(!(len % slice_len));
181 i2s->hw->end = false;
182 single_transfer = false;
184 sample_buff = (int16_t *)buf;
186 chunk_size = slice_len / 2;
187 remaing_size = len / 2;
188 transfer_size = len / 2;
191 memset(&lli0, 0, sizeof(DmacDesc));
192 memset(&lli1, 0, sizeof(DmacDesc));
198 for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
204 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
206 curr->src_addr = (uint32_t)&sample_buff[next_idx];
207 curr->dst_addr = (uint32_t)&SSC_THR;
208 curr->dsc_addr = (uint32_t)next;
209 curr->ctrla = I2S_TX_DMAC_CTRLA | (chunk_size & 0xffff);
210 curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
212 remaing_size -= chunk_size;
213 next_idx += chunk_size;
215 if (chunk_size > remaing_size)
220 dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG);
222 if (dmac_start(I2S_DMAC_CH) < 0)
224 LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
229 SSC_CR = BV(SSC_TXEN);
234 event_wait(&data_ready);
237 LOG_ERR("Error while streaming.\n");
243 LOG_INFO("Stop streaming.\n");
247 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
252 static void sam3_i2s_rxStop(I2s *i2s)
255 SSC_CR = BV(SSC_TXDIS);
258 static void sam3_i2s_rxWait(I2s *i2s)
263 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
272 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
277 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
282 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
286 single_transfer = true;
288 dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
289 dmac_configureDmac(I2S_DMAC_CH, len, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB);
290 dmac_start(I2S_DMAC_CH);
292 SSC_CR = BV(SSC_TXEN);
295 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
299 single_transfer = true;
301 dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
302 dmac_configureDmac(I2S_DMAC_CH, len, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB);
303 dmac_start(I2S_DMAC_CH);
305 SSC_CR = BV(SSC_RXEN);
308 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
312 SSC_CR = BV(SSC_TXEN);
313 while(!(SSC_SR & BV(SSC_TXRDY)))
320 static uint32_t sam3_i2s_read(struct I2s *i2s)
324 SSC_CR = BV(SSC_RXEN);
325 while(!(SSC_SR & BV(SSC_RXRDY)))
332 /* We divite for 2 because the min clock for i2s i MCLK/2 */
333 #define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
334 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
335 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
336 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
337 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
338 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
339 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
341 void i2s_init(I2s *i2s, int channel)
344 i2s->ctx.write = sam3_i2s_write;
345 i2s->ctx.tx_buf = sam3_i2s_txBuf;
346 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
347 i2s->ctx.tx_start = sam3_i2s_txStart;
348 i2s->ctx.tx_wait = sam3_i2s_txWait;
349 i2s->ctx.tx_stop = sam3_i2s_txStop;
351 i2s->ctx.read = sam3_i2s_read;
352 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
353 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
354 i2s->ctx.rx_start = sam3_i2s_rxStart;
355 i2s->ctx.rx_wait = sam3_i2s_rxWait;
356 i2s->ctx.rx_stop = sam3_i2s_rxStop;
358 DB(i2s->ctx._type = I2S_SAM3X;)
363 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
364 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
365 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
366 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
369 pmc_periphEnable(SSC_ID);
372 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
374 /* Set transmission clock */
375 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
376 /* Set the transmission mode:
377 * - the clk is generate from master clock
378 * - clock only during transfer
379 * - transmit Clock Gating Selection none
380 * - DELAY cycle insert before starting transmission
381 * - generate frame sync each 2*(PERIOD + 1) tramit clock
382 * - Receive start on falling edge RF
384 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
385 /* Set the transmission frame mode:
386 * - data len DATALEN + 1
387 * - word per frame DATNB + 1
388 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
389 * - DELAY cycle insert before starting transmission
391 * - Frame sync output selection negative
393 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
396 // Receiver should start on TX and take the clock from TK
397 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
398 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
401 SSC_IDR = 0xFFFFFFFF;
403 dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
404 event_initGeneric(&data_ready);