4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91SAM7S register definitions.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. Neither the name of the copyright holders nor the names of
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
61 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
63 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
64 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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67 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * For additional information see http://www.ethernut.de/
76 #define FLASH_BASE 0x100000UL
77 #define RAM_BASE 0x200000UL
79 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
80 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
81 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
82 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
83 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
84 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
85 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
86 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
87 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
89 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
90 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
91 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
92 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
93 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
94 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
95 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
96 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
97 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
98 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
100 #include "at91_aic.h"
101 #include "at91_pit.h"
102 #include "at91_pmc.h"
104 #include "at91_wdt.h"
105 #include "at91_rstc.h"
106 //TODO: add other peripherals
108 /** Peripheral Identifiers and Interrupts */
110 #define FIQ_ID 0 ///< Fast interrupt ID.
111 #define SYSC_ID 1 ///< System controller interrupt.
112 #define PIOA_ID 2 ///< Parallel I/O controller ID.
113 /* ID 3 is reserved */
114 #define ADC_ID 4 ///< Analog to digital converter ID.
115 #define SPI_ID 5 ///< Serial peripheral interface ID.
116 #define US0_ID 6 ///< USART 0 ID.
117 #define US1_ID 7 ///< USART 1 ID.
118 #define SSC_ID 8 ///< Synchronous serial controller ID.
119 #define TWI_ID 9 ///< Two-wire interface ID.
120 #define PWMC_ID 10 ///< PWM controller ID.
121 #define UDP_ID 11 ///< USB device port ID.
122 #define TC0_ID 12 ///< Timer 0 ID.
123 #define TC1_ID 13 ///< Timer 1 ID.
124 #define TC2_ID 14 ///< Timer 2 ID.
126 #define IRQ0_ID 30 ///< External interrupt 0 ID.
127 #define IRQ1_ID 31 ///< External interrupt 1 ID.
130 #warning Revise me after this line!
132 #define PERIPH_RPR_OFF 0x00000100 ///< Receive pointer register offset.
133 #define PERIPH_RCR_OFF 0x00000104 ///< Receive counter register offset.
134 #define PERIPH_TPR_OFF 0x00000108 ///< Transmit pointer register offset.
135 #define PERIPH_TCR_OFF 0x0000010C ///< Transmit counter register offset.
136 #define PERIPH_RNPR_OFF 0x00000110 ///< Receive next pointer register offset.
137 #define PERIPH_RNCR_OFF 0x00000114 ///< Receive next counter register offset.
138 #define PERIPH_TNPR_OFF 0x00000118 ///< Transmit next pointer register offset.
139 #define PERIPH_TNCR_OFF 0x0000011C ///< Transmit next counter register offset.
140 #define PERIPH_PTCR_OFF 0x00000120 ///< PDC transfer control register offset.
141 #define PERIPH_PTSR_OFF 0x00000124 ///< PDC transfer status register offset.
143 #define PDC_RXTEN 0x00000001 ///< Receiver transfer enable.
144 #define PDC_RXTDIS 0x00000002 ///< Receiver transfer disable.
145 #define PDC_TXTEN 0x00000100 ///< Transmitter transfer enable.
146 #define PDC_TXTDIS 0x00000200 ///< Transmitter transfer disable.
151 #define USART_HAS_PDC
153 #define PIO_HAS_MULTIDRIVER
154 #define PIO_HAS_PULLUP
155 #define PIO_HAS_PERIPHERALSELECT
156 #define PIO_HAS_OUTPUTWRITEENABLE
159 /** Historical SPI0 Peripheral Multiplexing Names */
161 #define SPI0_NPCS0_PA12A 12 ///< Port bit number on PIO-A Perpheral A.
162 #define SPI0_NPCS1_PA13A 13 ///< Port bit number on PIO-A Perpheral A.
163 #define SPI0_NPCS1_PA07B 7 ///< Port bit number on PIO-A Perpheral B.
164 #define SPI0_NPCS1_PB13B 13 ///< Port bit number on PIO-B Perpheral B.
165 #define SPI0_NPCS2_PA14A 14 ///< Port bit number on PIO-A Perpheral A.
166 #define SPI0_NPCS2_PA08B 8 ///< Port bit number on PIO-A Perpheral B.
167 #define SPI0_NPCS2_PB14B 14 ///< Port bit number on PIO-B Perpheral B.
168 #define SPI0_NPCS3_PA15A 15 ///< Port bit number on PIO-A Perpheral A.
169 #define SPI0_NPCS3_PA09B 9 ///< Port bit number on PIO-A Perpheral B.
170 #define SPI0_NPCS3_PB17B 17 ///< Port bit number on PIO-B Perpheral B.
171 #define SPI0_MISO_PA16A 16 ///< Port bit number on PIO-A Perpheral A.
172 #define SPI0_MOSI_PA17A 17 ///< Port bit number on PIO-A Perpheral A.
173 #define SPI0_SPCK_PA18A 18 ///< Port bit number on PIO-A Perpheral A.
176 /** USART Peripheral Multiplexing */
189 #define PB23_DCD1_B 23
190 #define PB24_DSR1_B 24
191 #define PB25_DTR1_B 25
192 #define PB26_RI1_B 26
195 /** SPI Peripheral Multiplexing */
197 #define PA16_SPI0_MISO_A 16
198 #define PA17_SPI0_MOSI_A 17
199 #define PA18_SPI0_SPCK_A 18
200 #define PA12_SPI0_NPCS0_A 12
201 #define PA13_SPI0_NPCS1_A 13
202 #define PA7_SPI0_NPCS1_B 7
203 #define PA14_SPI0_NPCS2_A 14
204 #define PB14_SPI0_NPCS2_B 14
205 #define PA8_SPI0_NPCS2_B 8
206 #define PA15_SPI0_NPCS3_A 15
207 #define PA9_SPI0_NPCS3_B 9
209 #define SPI0_PINS _BV(PA16_SPI0_MISO_A) | _BV(PA17_SPI0_MOSI_A) | _BV(PA18_SPI0_SPCK_A)
210 #define SPI0_PIO_BASE PIOA_BASE
211 #define SPI0_PSR_OFF PIO_ASR_OFF
213 #define SPI0_CS0_PIN _BV(PA12_SPI0_NPCS0_A)
214 #define SPI0_CS0_PIO_BASE PIOA_BASE
215 #define SPI0_CS0_PSR_OFF PIO_ASR_OFF
218 #define SPI0_CS1_PIN _BV(PA13_SPI0_NPCS1_A)
219 #define SPI0_CS1_PIO_BASE PIOA_BASE
220 #define SPI0_CS1_PSR_OFF PIO_ASR_OFF
224 #define SPI0_CS2_PIN _BV(PA14_SPI0_NPCS2_A)
225 #define SPI0_CS2_PIO_BASE PIOA_BASE
226 #define SPI0_CS2_PSR_OFF PIO_ASR_OFF
230 #define SPI0_CS3_PIN _BV(PA15_SPI0_NPCS3_A)
231 #define SPI0_CS3_PIO_BASE PIOA_BASE
232 #define SPI0_CS3_PSR_OFF PIO_ASR_OFF
235 #define PA24_SPI1_MISO_B 24
236 #define PA23_SPI1_MOSI_B 23
237 #define PA22_SPI1_SPCK_B 22
238 #define PA21_SPI1_NPCS0_B 21
239 #define PA25_SPI1_NPCS1_B 25
240 #define PB13_SPI0_NPCS1_B 13
241 #define PA2_SPI1_NPCS1_B 2
242 #define PB10_SPI1_NPCS1_B 10
243 #define PA26_SPI1_NPCS2_B 26
244 #define PA3_SPI1_NPCS2_B 3
245 #define PB11_SPI1_NPCS2_B 11
246 #define PB17_SPI0_NPCS3_B 17
247 #define PA4_SPI1_NPCS3_B 4
248 #define PA29_SPI1_NPCS3_B 29
249 #define PB16_SPI1_NPCS3_B 16
251 #define SPI1_PINS _BV(PA24_SPI1_MISO_B) | _BV(PA23_SPI1_MOSI_B) | _BV(PA22_SPI1_SPCK_B)
252 #define SPI1_PIO_BASE PIOA_BASE
253 #define SPI1_PSR_OFF PIO_BSR_OFF
255 #define SPI1_CS0_PIN _BV(PA21_SPI1_NPCS0_B)
256 #define SPI1_CS0_PIO_BASE PIOA_BASE
257 #define SPI1_CS0_PSR_OFF PIO_BSR_OFF
260 #define SPI1_CS1_PIN _BV(PA25_SPI1_NPCS1_B)
261 #define SPI1_CS1_PIO_BASE PIOA_BASE
262 #define SPI1_CS1_PSR_OFF PIO_BSR_OFF
266 #define SPI1_CS2_PIN _BV(PA26_SPI1_NPCS2_B)
267 #define SPI1_CS2_PIO_BASE PIOA_BASE
268 #define SPI1_CS2_PSR_OFF PIO_BSR_OFF
272 #define SPI1_CS3_PIN _BV(PA29_SPI1_NPCS3_B)
273 #define SPI1_CS3_PIO_BASE PIOA_BASE
274 #define SPI1_CS3_PSR_OFF PIO_BSR_OFF
279 /** EMAC Interface Peripheral Multiplexing */
281 #define PB0_ETXCK_EREFCK_A 0
282 #define PB1_ETXEN_A 1
288 #define PB7_ERXER_A 7
290 #define PB9_EMDIO_A 9
291 #define PB10_ETX2_A 10
292 #define PB11_ETX3_A 11
293 #define PB12_ETXER_A 12
294 #define PB13_ERX2_A 13
295 #define PB14_ERX3_A 14
296 #define PB15_ERXDV_ECRSDV_A 15
297 #define PB16_ECOL_A 16
298 #define PB17_ERXCK_A 17
299 #define PB18_EF100_A 18
302 /** Debug Unit Peripheral Multiplexing */
304 #define PA27_DRXD_A 27
305 #define PA28_DTXD_A 28
308 /** Synchronous Serial Controller Peripheral Multiplexing */
310 #define PA23_TD_A 23 ///< Transmit data pin.
311 #define PA24_RD_A 24 ///< Receive data pin.
312 #define PA22_TK_A 22 ///< Transmit clock pin.
313 #define PA25_RK_A 25 ///< Receive clock pin.
314 #define PA21_TF_A 21 ///< Transmit frame sync. pin.
315 #define PA26_RF_A 26 ///< Receive frame sync. pin.
318 /** Two Wire Interface Peripheral Multiplexing */
320 #define PA10_TWD_A 10 ///< Two wire serial data pin.
321 #define PA11_TWCK_A 11 ///< Two wire serial clock pin.
324 /** Timer/Counter Peripheral Multiplexing */
326 #define PB23_TIOA0_A 23
327 #define PB24_TIOB0_A 24
328 #define PB12_TCLK0_B 12
330 #define PB25_TIOA1_A 25
331 #define PB26_TIOB1_A 26
332 #define PB19_TCLK1_B 19
334 #define PB27_TIOA2_A 27
335 #define PB28_TIOB2_A 28
336 #define PA15_TCLK2_B 15
339 /** Clocks, Oscillators and PLLs Peripheral Multiplexing */
342 #define PB20_PCK0_B 20
343 #define PA13_PCK1_B 13
344 #define PB29_PCK1_A 29
345 #define PB21_PCK1_B 21
346 #define PA30_PCK2_B 30
347 #define PB30_PCK2_A 30
348 #define PB22_PCK2_B 22
349 #define PA27_PCK3_B 27
352 /** Advanced Interrupt Controller Peripheral Multiplexing */
354 #define PA29_FIQ_A 29
355 #define PA30_IRQ0_A 30
356 #define PA14_IRQ1_B 14
359 /** ADC Interface Peripheral Multiplexing */
361 #define PB18_ADTRG_B 18 ///< ADC trigger pin.
364 /** CAN Interface Peripheral Multiplexing */
366 #define PA19_CANRX_A 19
367 #define PA20_CANTX_A 20
370 /** PWM Peripheral Multiplexing */
372 #define PB19_PWM0_A 19
373 #define PB27_PWM0_B 27
374 #define PB20_PWM1_A 20
375 #define PB28_PWM1_B 28
376 #define PB21_PWM2_A 21
377 #define PB29_PWM2_B 29
378 #define PB22_PWM3_A 22
379 #define PB30_PWM3_B 30
382 #endif /* AT91SAM7S_H */