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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 PWM hardware definitions.
40 * The following are defines for the PWM register offsets.
42 #define PWM_O_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< PWM Master Control
43 #define PWM_O_SYNC (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< PWM Time Base Sync
44 #define PWM_O_ENABLE (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< PWM Output Enable
45 #define PWM_O_INVERT (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< PWM Output Inversion
46 #define PWM_O_FAULT (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< PWM Output Fault
47 #define PWM_O_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< PWM Interrupt Enable
48 #define PWM_O_RIS (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< PWM Raw Interrupt Status
49 #define PWM_O_ISC (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< PWM Interrupt Status and Clear
50 #define PWM_O_STATUS (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< PWM Status
51 #define PWM_O_FAULTVAL (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< PWM Fault Condition Value
52 #define PWM_O_ENUPD (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< PWM Enable Update
53 #define PWM_O_0_CTL (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 Control
54 #define PWM_O_0_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000044))) //< PWM0 Interrupt and Trigger Enable
55 #define PWM_O_0_RIS (*((reg32_t *)(PWMC_BASE + 0x00000048))) //< PWM0 Raw Interrupt Status
56 #define PWM_O_0_ISC (*((reg32_t *)(PWMC_BASE + 0x0000004C))) //< PWM0 Interrupt Status and Clear
57 #define PWM_O_0_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000050))) //< PWM0 Load
58 #define PWM_O_0_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000054))) //< PWM0 Counter
59 #define PWM_O_0_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000058))) //< PWM0 Compare A
60 #define PWM_O_0_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000005C))) //< PWM0 Compare B
61 #define PWM_O_0_GENA (*((reg32_t *)(PWMC_BASE + 0x00000060))) //< PWM0 Generator A Control
62 #define PWM_O_0_GENB (*((reg32_t *)(PWMC_BASE + 0x00000064))) //< PWM0 Generator B Control
63 #define PWM_O_0_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000068))) //< PWM0 Dead-Band Control
64 #define PWM_O_0_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000006C))) //< PWM0 Dead-Band Rising-Edge Delay
65 #define PWM_O_0_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000070))) //< PWM0 Dead-Band Falling-Edge-Delay
66 #define PWM_O_0_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000074))) //< PWM0 Fault Source 0
67 #define PWM_O_0_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000078))) //< PWM0 Fault Source 1
68 #define PWM_O_0_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000007C))) //< PWM0 Minimum Fault Period
69 #define PWM_O_1_CTL (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 Control
70 #define PWM_O_1_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000084))) //< PWM1 Interrupt and Trigger Enable
71 #define PWM_O_1_RIS (*((reg32_t *)(PWMC_BASE + 0x00000088))) //< PWM1 Raw Interrupt Status
72 #define PWM_O_1_ISC (*((reg32_t *)(PWMC_BASE + 0x0000008C))) //< PWM1 Interrupt Status and Clear
73 #define PWM_O_1_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000090))) //< PWM1 Load
74 #define PWM_O_1_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000094))) //< PWM1 Counter
75 #define PWM_O_1_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000098))) //< PWM1 Compare A
76 #define PWM_O_1_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000009C))) //< PWM1 Compare B
77 #define PWM_O_1_GENA (*((reg32_t *)(PWMC_BASE + 0x000000A0))) //< PWM1 Generator A Control
78 #define PWM_O_1_GENB (*((reg32_t *)(PWMC_BASE + 0x000000A4))) //< PWM1 Generator B Control
79 #define PWM_O_1_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000A8))) //< PWM1 Dead-Band Control
80 #define PWM_O_1_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000AC))) //< PWM1 Dead-Band Rising-Edge Delay
81 #define PWM_O_1_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000B0))) //< PWM1 Dead-Band Falling-Edge-Delay
82 #define PWM_O_1_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000B4))) //< PWM1 Fault Source 0
83 #define PWM_O_1_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000B8))) //< PWM1 Fault Source 1
84 #define PWM_O_1_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000BC))) //< PWM1 Minimum Fault Period
85 #define PWM_O_2_CTL (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 Control
86 #define PWM_O_2_INTEN (*((reg32_t *)(PWMC_BASE + 0x000000C4))) //< PWM2 Interrupt and Trigger Enable
87 #define PWM_O_2_RIS (*((reg32_t *)(PWMC_BASE + 0x000000C8))) //< PWM2 Raw Interrupt Status
88 #define PWM_O_2_ISC (*((reg32_t *)(PWMC_BASE + 0x000000CC))) //< PWM2 Interrupt Status and Clear
89 #define PWM_O_2_LOAD (*((reg32_t *)(PWMC_BASE + 0x000000D0))) //< PWM2 Load
90 #define PWM_O_2_COUNT (*((reg32_t *)(PWMC_BASE + 0x000000D4))) //< PWM2 Counter
91 #define PWM_O_2_CMPA (*((reg32_t *)(PWMC_BASE + 0x000000D8))) //< PWM2 Compare A
92 #define PWM_O_2_CMPB (*((reg32_t *)(PWMC_BASE + 0x000000DC))) //< PWM2 Compare B
93 #define PWM_O_2_GENA (*((reg32_t *)(PWMC_BASE + 0x000000E0))) //< PWM2 Generator A Control
94 #define PWM_O_2_GENB (*((reg32_t *)(PWMC_BASE + 0x000000E4))) //< PWM2 Generator B Control
95 #define PWM_O_2_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000E8))) //< PWM2 Dead-Band Control
96 #define PWM_O_2_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000EC))) //< PWM2 Dead-Band Rising-Edge Delay
97 #define PWM_O_2_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000F0))) //< PWM2 Dead-Band Falling-Edge-Delay
98 #define PWM_O_2_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000F4))) //< PWM2 Fault Source 0
99 #define PWM_O_2_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000F8))) //< PWM2 Fault Source 1
100 #define PWM_O_2_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000FC))) //< PWM2 Minimum Fault Period
101 #define PWM_O_3_CTL (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 Control
102 #define PWM_O_3_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000104))) //< PWM3 Interrupt and Trigger Enable
103 #define PWM_O_3_RIS (*((reg32_t *)(PWMC_BASE + 0x00000108))) //< PWM3 Raw Interrupt Status
104 #define PWM_O_3_ISC (*((reg32_t *)(PWMC_BASE + 0x0000010C))) //< PWM3 Interrupt Status and Clear
105 #define PWM_O_3_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000110))) //< PWM3 Load
106 #define PWM_O_3_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000114))) //< PWM3 Counter
107 #define PWM_O_3_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000118))) //< PWM3 Compare A
108 #define PWM_O_3_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000011C))) //< PWM3 Compare B
109 #define PWM_O_3_GENA (*((reg32_t *)(PWMC_BASE + 0x00000120))) //< PWM3 Generator A Control
110 #define PWM_O_3_GENB (*((reg32_t *)(PWMC_BASE + 0x00000124))) //< PWM3 Generator B Control
111 #define PWM_O_3_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000128))) //< PWM3 Dead-Band Control
112 #define PWM_O_3_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000012C))) //< PWM3 Dead-Band Rising-Edge Delay
113 #define PWM_O_3_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000130))) //< PWM3 Dead-Band Falling-Edge-Delay
114 #define PWM_O_3_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000134))) //< PWM3 Fault Source 0
115 #define PWM_O_3_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000138))) //< PWM3 Fault Source 1
116 #define PWM_O_3_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000013C))) //< PWM3 Minimum Fault Period
117 #define PWM_O_0_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 Fault Pin Logic Sense
118 #define PWM_O_0_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000804))) //< PWM0 Fault Status 0
119 #define PWM_O_0_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000808))) //< PWM0 Fault Status 1
120 #define PWM_O_1_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 Fault Pin Logic Sense
121 #define PWM_O_1_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000884))) //< PWM1 Fault Status 0
122 #define PWM_O_1_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000888))) //< PWM1 Fault Status 1
123 #define PWM_O_2_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 Fault Pin Logic Sense
124 #define PWM_O_2_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000904))) //< PWM2 Fault Status 0
125 #define PWM_O_2_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000908))) //< PWM2 Fault Status 1
126 #define PWM_O_3_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 Fault Pin Logic Sense
127 #define PWM_O_3_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000984))) //< PWM3 Fault Status 0
128 #define PWM_O_3_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000988))) //< PWM3 Fault Status 1
131 * Defines for the bit fields in the PWM_O_CTL register.
133 #define PWM_CTL_GLOBALSYNC3 3 //< Update PWM Generator 3
134 #define PWM_CTL_GLOBALSYNC2 2 //< Update PWM Generator 2
135 #define PWM_CTL_GLOBALSYNC1 1 //< Update PWM Generator 1
136 #define PWM_CTL_GLOBALSYNC0 0 //< Update PWM Generator 0
139 * Defines for the bit fields in the PWM_O_SYNC register.
141 #define PWM_SYNC_SYNC3 3 //< Reset Generator 3 Counter
142 #define PWM_SYNC_SYNC2 2 //< Reset Generator 2 Counter
143 #define PWM_SYNC_SYNC1 1 //< Reset Generator 1 Counter
144 #define PWM_SYNC_SYNC0 0 //< Reset Generator 0 Counter
147 * Defines for the bit fields in the PWM_O_ENABLE register.
149 #define PWM_ENABLE_PWM7EN 7 //< PWM7 Output Enable
150 #define PWM_ENABLE_PWM6EN 6 //< PWM6 Output Enable
151 #define PWM_ENABLE_PWM5EN 5 //< PWM5 Output Enable
152 #define PWM_ENABLE_PWM4EN 4 //< PWM4 Output Enable
153 #define PWM_ENABLE_PWM3EN 3 //< PWM3 Output Enable
154 #define PWM_ENABLE_PWM2EN 2 //< PWM2 Output Enable
155 #define PWM_ENABLE_PWM1EN 1 //< PWM1 Output Enable
156 #define PWM_ENABLE_PWM0EN 0 //< PWM0 Output Enable
159 * Defines for the bit fields in the PWM_O_INVERT register.
161 #define PWM_INVERT_PWM7INV 7 //< Invert PWM7 Signal
162 #define PWM_INVERT_PWM6INV 6 //< Invert PWM6 Signal
163 #define PWM_INVERT_PWM5INV 5 //< Invert PWM5 Signal
164 #define PWM_INVERT_PWM4INV 4 //< Invert PWM4 Signal
165 #define PWM_INVERT_PWM3INV 3 //< Invert PWM3 Signal
166 #define PWM_INVERT_PWM2INV 2 //< Invert PWM2 Signal
167 #define PWM_INVERT_PWM1INV 1 //< Invert PWM1 Signal
168 #define PWM_INVERT_PWM0INV 0 //< Invert PWM0 Signal
171 * Defines for the bit fields in the PWM_O_FAULT register.
173 #define PWM_FAULT_FAULT7 7 //< PWM7 Fault
174 #define PWM_FAULT_FAULT6 6 //< PWM6 Fault
175 #define PWM_FAULT_FAULT5 5 //< PWM5 Fault
176 #define PWM_FAULT_FAULT4 4 //< PWM4 Fault
177 #define PWM_FAULT_FAULT3 3 //< PWM3 Fault
178 #define PWM_FAULT_FAULT2 2 //< PWM2 Fault
179 #define PWM_FAULT_FAULT1 1 //< PWM1 Fault
180 #define PWM_FAULT_FAULT0 0 //< PWM0 Fault
183 * Defines for the bit fields in the PWM_O_INTEN register.
185 #define PWM_INTEN_INTFAULT3 19 //< Interrupt Fault 3
186 #define PWM_INTEN_INTFAULT2 18 //< Interrupt Fault 2
187 #define PWM_INTEN_INTFAULT1 17 //< Interrupt Fault 1
188 #define PWM_INTEN_INTFAULT 16 //< Fault Interrupt Enable
189 #define PWM_INTEN_INTFAULT0 16 //< Interrupt Fault 0
190 #define PWM_INTEN_INTPWM3 3 //< PWM3 Interrupt Enable
191 #define PWM_INTEN_INTPWM2 2 //< PWM2 Interrupt Enable
192 #define PWM_INTEN_INTPWM1 1 //< PWM1 Interrupt Enable
193 #define PWM_INTEN_INTPWM0 0 //< PWM0 Interrupt Enable
196 * Defines for the bit fields in the PWM_O_RIS register.
198 #define PWM_RIS_INTFAULT3 19 //< Interrupt Fault PWM 3
199 #define PWM_RIS_INTFAULT2 18 //< Interrupt Fault PWM 2
200 #define PWM_RIS_INTFAULT1 17 //< Interrupt Fault PWM 1
201 #define PWM_RIS_INTFAULT0 16 //< Interrupt Fault PWM 0
202 #define PWM_RIS_INTFAULT 16 //< Fault Interrupt Asserted
203 #define PWM_RIS_INTPWM3 3 //< PWM3 Interrupt Asserted
204 #define PWM_RIS_INTPWM2 2 //< PWM2 Interrupt Asserted
205 #define PWM_RIS_INTPWM1 1 //< PWM1 Interrupt Asserted
206 #define PWM_RIS_INTPWM0 0 //< PWM0 Interrupt Asserted
209 * Defines for the bit fields in the PWM_O_ISC register.
211 #define PWM_ISC_INTFAULT3 19 //< FAULT3 Interrupt Asserted
212 #define PWM_ISC_INTFAULT2 18 //< FAULT2 Interrupt Asserted
213 #define PWM_ISC_INTFAULT1 17 //< FAULT1 Interrupt Asserted
214 #define PWM_ISC_INTFAULT 16 //< Fault Interrupt Asserted
215 #define PWM_ISC_INTFAULT0 16 //< FAULT0 Interrupt Asserted
216 #define PWM_ISC_INTPWM3 3 //< PWM3 Interrupt Status
217 #define PWM_ISC_INTPWM2 2 //< PWM2 Interrupt Status
218 #define PWM_ISC_INTPWM1 1 //< PWM1 Interrupt Status
219 #define PWM_ISC_INTPWM0 0 //< PWM0 Interrupt Status
222 * Defines for the bit fields in the PWM_O_STATUS register.
224 #define PWM_STATUS_FAULT3 3 //< Generator 3 Fault Status
225 #define PWM_STATUS_FAULT2 2 //< Generator 2 Fault Status
226 #define PWM_STATUS_FAULT1 1 //< Generator 1 Fault Status
227 #define PWM_STATUS_FAULT0 0 //< Generator 0 Fault Status
230 * Defines for the bit fields in the PWM_O_FAULTVAL register.
232 #define PWM_FAULTVAL_PWM7 7 //< PWM7 Fault Value
233 #define PWM_FAULTVAL_PWM6 6 //< PWM6 Fault Value
234 #define PWM_FAULTVAL_PWM5 5 //< PWM5 Fault Value
235 #define PWM_FAULTVAL_PWM4 4 //< PWM4 Fault Value
236 #define PWM_FAULTVAL_PWM3 3 //< PWM3 Fault Value
237 #define PWM_FAULTVAL_PWM2 2 //< PWM2 Fault Value
238 #define PWM_FAULTVAL_PWM1 1 //< PWM1 Fault Value
239 #define PWM_FAULTVAL_PWM0 0 //< PWM0 Fault Value
242 * Defines for the bit fields in the PWM_O_ENUPD register.
244 #define PWM_ENUPD_ENUPD7_M 0x0000C000 //< PWM7 Enable Update Mode
245 #define PWM_ENUPD_ENUPD7_IMM 0x00000000 //< Immediate
246 #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 //< Locally Synchronized
247 #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 //< Globally Synchronized
248 #define PWM_ENUPD_ENUPD6_M 0x00003000 //< PWM6 Enable Update Mode
249 #define PWM_ENUPD_ENUPD6_IMM 0x00000000 //< Immediate
250 #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 //< Locally Synchronized
251 #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 //< Globally Synchronized
252 #define PWM_ENUPD_ENUPD5_M 0x00000C00 //< PWM5 Enable Update Mode
253 #define PWM_ENUPD_ENUPD5_IMM 0x00000000 //< Immediate
254 #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 //< Locally Synchronized
255 #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 //< Globally Synchronized
256 #define PWM_ENUPD_ENUPD4_M 0x00000300 //< PWM4 Enable Update Mode
257 #define PWM_ENUPD_ENUPD4_IMM 0x00000000 //< Immediate
258 #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 //< Locally Synchronized
259 #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 //< Globally Synchronized
260 #define PWM_ENUPD_ENUPD3_M 0x000000C0 //< PWM3 Enable Update Mode
261 #define PWM_ENUPD_ENUPD3_IMM 0x00000000 //< Immediate
262 #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 //< Locally Synchronized
263 #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 //< Globally Synchronized
264 #define PWM_ENUPD_ENUPD2_M 0x00000030 //< PWM2 Enable Update Mode
265 #define PWM_ENUPD_ENUPD2_IMM 0x00000000 //< Immediate
266 #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 //< Locally Synchronized
267 #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 //< Globally Synchronized
268 #define PWM_ENUPD_ENUPD1_M 0x0000000C //< PWM1 Enable Update Mode
269 #define PWM_ENUPD_ENUPD1_IMM 0x00000000 //< Immediate
270 #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 //< Locally Synchronized
271 #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C //< Globally Synchronized
272 #define PWM_ENUPD_ENUPD0_M 0x00000003 //< PWM0 Enable Update Mode
273 #define PWM_ENUPD_ENUPD0_IMM 0x00000000 //< Immediate
274 #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 //< Locally Synchronized
275 #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 //< Globally Synchronized
278 * Defines for the bit fields in the PWM_O_X_CTL register.
280 #define PWM_X_CTL_LATCH 0x00040000 //< Latch Fault Input
281 #define PWM_X_CTL_MINFLTPER 0x00020000 //< Minimum Fault Period
282 #define PWM_X_CTL_FLTSRC 0x00010000 //< Fault Condition Source
283 #define PWM_X_CTL_DBFALLUPD_M 0x0000C000 //< PWMnDBFALL Update Mode
284 #define PWM_X_CTL_DBFALLUPD_I 0x00000000 //< Immediate
285 #define PWM_X_CTL_DBFALLUPD_LS 0x00008000 //< Locally Synchronized
286 #define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 //< Globally Synchronized
287 #define PWM_X_CTL_DBRISEUPD_M 0x00003000 //< PWMnDBRISE Update Mode
288 #define PWM_X_CTL_DBRISEUPD_I 0x00000000 //< Immediate
289 #define PWM_X_CTL_DBRISEUPD_LS 0x00002000 //< Locally Synchronized
290 #define PWM_X_CTL_DBRISEUPD_GS 0x00003000 //< Globally Synchronized
291 #define PWM_X_CTL_DBCTLUPD_M 0x00000C00 //< PWMnDBCTL Update Mode
292 #define PWM_X_CTL_DBCTLUPD_I 0x00000000 //< Immediate
293 #define PWM_X_CTL_DBCTLUPD_LS 0x00000800 //< Locally Synchronized
294 #define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 //< Globally Synchronized
295 #define PWM_X_CTL_GENBUPD_M 0x00000300 //< PWMnGENB Update Mode
296 #define PWM_X_CTL_GENBUPD_I 0x00000000 //< Immediate
297 #define PWM_X_CTL_GENBUPD_LS 0x00000200 //< Locally Synchronized
298 #define PWM_X_CTL_GENBUPD_GS 0x00000300 //< Globally Synchronized
299 #define PWM_X_CTL_GENAUPD_M 0x000000C0 //< PWMnGENA Update Mode
300 #define PWM_X_CTL_GENAUPD_I 0x00000000 //< Immediate
301 #define PWM_X_CTL_GENAUPD_LS 0x00000080 //< Locally Synchronized
302 #define PWM_X_CTL_GENAUPD_GS 0x000000C0 //< Globally Synchronized
303 #define PWM_X_CTL_CMPBUPD 0x00000020 //< Comparator B Update Mode
304 #define PWM_X_CTL_CMPAUPD 0x00000010 //< Comparator A Update Mode
305 #define PWM_X_CTL_LOADUPD 0x00000008 //< Load Register Update Mode
306 #define PWM_X_CTL_DEBUG 0x00000004 //< Debug Mode
307 #define PWM_X_CTL_MODE 0x00000002 //< Counter Mode
308 #define PWM_X_CTL_ENABLE 0x00000001 //< PWM Block Enable
311 * Defines for the bit fields in the PWM_O_X_INTEN register.
313 #define PWM_X_INTEN_TRCMPBD 0x00002000 //< Trigger for Counter=PWMnCMPB Down
314 #define PWM_X_INTEN_TRCMPBU 0x00001000 //< Trigger for Counter=PWMnCMPB Up
315 #define PWM_X_INTEN_TRCMPAD 0x00000800 //< Trigger for Counter=PWMnCMPA Down
316 #define PWM_X_INTEN_TRCMPAU 0x00000400 //< Trigger for Counter=PWMnCMPA Up
317 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 //< Trigger for Counter=PWMnLOAD
318 #define PWM_X_INTEN_TRCNTZERO 0x00000100 //< Trigger for Counter=0
319 #define PWM_X_INTEN_INTCMPBD 0x00000020 //< Interrupt for Counter=PWMnCMPB Down
320 #define PWM_X_INTEN_INTCMPBU 0x00000010 //< Interrupt for Counter=PWMnCMPB Up
321 #define PWM_X_INTEN_INTCMPAD 0x00000008 //< Interrupt for Counter=PWMnCMPA Down
322 #define PWM_X_INTEN_INTCMPAU 0x00000004 //< Interrupt for Counter=PWMnCMPA Up
323 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 //< Interrupt for Counter=PWMnLOAD
324 #define PWM_X_INTEN_INTCNTZERO 0x00000001 //< Interrupt for Counter=0
327 * Defines for the bit fields in the PWM_O_X_RIS register.
329 #define PWM_X_RIS_INTCMPBD 0x00000020 //< Comparator B Down Interrupt Status
330 #define PWM_X_RIS_INTCMPBU 0x00000010 //< Comparator B Up Interrupt Status
331 #define PWM_X_RIS_INTCMPAD 0x00000008 //< Comparator A Down Interrupt Status
332 #define PWM_X_RIS_INTCMPAU 0x00000004 //< Comparator A Up Interrupt Status
333 #define PWM_X_RIS_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt Status
334 #define PWM_X_RIS_INTCNTZERO 0x00000001 //< Counter=0 Interrupt Status
337 * Defines for the bit fields in the PWM_O_X_ISC register.
339 #define PWM_X_ISC_INTCMPBD 0x00000020 //< Comparator B Down Interrupt
340 #define PWM_X_ISC_INTCMPBU 0x00000010 //< Comparator B Up Interrupt
341 #define PWM_X_ISC_INTCMPAD 0x00000008 //< Comparator A Down Interrupt
342 #define PWM_X_ISC_INTCMPAU 0x00000004 //< Comparator A Up Interrupt
343 #define PWM_X_ISC_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt
344 #define PWM_X_ISC_INTCNTZERO 0x00000001 //< Counter=0 Interrupt
347 * Defines for the bit fields in the PWM_O_X_LOAD register.
349 #define PWM_X_LOAD_M 0x0000FFFF //< Counter Load Value
350 #define PWM_X_LOAD_S 0
353 * Defines for the bit fields in the PWM_O_X_COUNT register.
355 #define PWM_X_COUNT_M 0x0000FFFF //< Counter Value
356 #define PWM_X_COUNT_S 0
359 * Defines for the bit fields in the PWM_O_X_CMPA register.
361 #define PWM_X_CMPA_M 0x0000FFFF //< Comparator A Value
362 #define PWM_X_CMPA_S 0
365 * Defines for the bit fields in the PWM_O_X_CMPB register.
367 #define PWM_X_CMPB_M 0x0000FFFF //< Comparator B Value
368 #define PWM_X_CMPB_S 0
371 * Defines for the bit fields in the PWM_O_X_GENA register.
373 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down
374 #define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 //< Do nothing
375 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 //< Invert pwmA
376 #define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 //< Drive pwmA Low
377 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 //< Drive pwmA High
378 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up
379 #define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 //< Do nothing
380 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 //< Invert pwmA
381 #define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 //< Drive pwmA Low
382 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 //< Drive pwmA High
383 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down
384 #define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 //< Do nothing
385 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 //< Invert pwmA
386 #define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 //< Drive pwmA Low
387 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 //< Drive pwmA High
388 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up
389 #define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 //< Do nothing
390 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 //< Invert pwmA
391 #define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 //< Drive pwmA Low
392 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 //< Drive pwmA High
393 #define PWM_X_GENA_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD
394 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 //< Do nothing
395 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 //< Invert pwmA
396 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 //< Drive pwmA Low
397 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C //< Drive pwmA High
398 #define PWM_X_GENA_ACTZERO_M 0x00000003 //< Action for Counter=0
399 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 //< Do nothing
400 #define PWM_X_GENA_ACTZERO_INV 0x00000001 //< Invert pwmA
401 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 //< Drive pwmA Low
402 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 //< Drive pwmA High
405 * Defines for the bit fields in the PWM_O_X_GENB register.
407 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down
408 #define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 //< Do nothing
409 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 //< Invert pwmB
410 #define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 //< Drive pwmB Low
411 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 //< Drive pwmB High
412 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up
413 #define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 //< Do nothing
414 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 //< Invert pwmB
415 #define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 //< Drive pwmB Low
416 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 //< Drive pwmB High
417 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down
418 #define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 //< Do nothing
419 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 //< Invert pwmB
420 #define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 //< Drive pwmB Low
421 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 //< Drive pwmB High
422 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up
423 #define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 //< Do nothing
424 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 //< Invert pwmB
425 #define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 //< Drive pwmB Low
426 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 //< Drive pwmB High
427 #define PWM_X_GENB_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD
428 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 //< Do nothing
429 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 //< Invert pwmB
430 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 //< Drive pwmB Low
431 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C //< Drive pwmB High
432 #define PWM_X_GENB_ACTZERO_M 0x00000003 //< Action for Counter=0
433 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 //< Do nothing
434 #define PWM_X_GENB_ACTZERO_INV 0x00000001 //< Invert pwmB
435 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 //< Drive pwmB Low
436 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 //< Drive pwmB High
439 * Defines for the bit fields in the PWM_O_X_DBCTL register.
441 #define PWM_X_DBCTL_ENABLE 0x00000001 //< Dead-Band Generator Enable
443 * Defines for the bit fields in the PWM_O_X_DBRISE register.
445 #define PWM_X_DBRISE_DELAY_M 0x00000FFF //< Dead-Band Rise Delay
446 #define PWM_X_DBRISE_DELAY_S 0
449 * Defines for the bit fields in the PWM_O_X_DBFALL register.
451 #define PWM_X_DBFALL_DELAY_M 0x00000FFF //< Dead-Band Fall Delay
452 #define PWM_X_DBFALL_DELAY_S 0
455 * Defines for the bit fields in the PWM_O_X_FLTSRC0 register.
457 #define PWM_X_FLTSRC0_FAULT3 0x00000008 //< Fault3 Input
458 #define PWM_X_FLTSRC0_FAULT2 0x00000004 //< Fault2 Input
459 #define PWM_X_FLTSRC0_FAULT1 0x00000002 //< Fault1 Input
460 #define PWM_X_FLTSRC0_FAULT0 0x00000001 //< Fault0 Input
463 * The following are defines for the bit fields in the PWM_O_X_FLTSRC1 register.
465 #define PWM_X_FLTSRC1_DCMP7 0x00000080 //< Digital Comparator 7
466 #define PWM_X_FLTSRC1_DCMP6 0x00000040 //< Digital Comparator 6
467 #define PWM_X_FLTSRC1_DCMP5 0x00000020 //< Digital Comparator 5
468 #define PWM_X_FLTSRC1_DCMP4 0x00000010 //< Digital Comparator 4
469 #define PWM_X_FLTSRC1_DCMP3 0x00000008 //< Digital Comparator 3
470 #define PWM_X_FLTSRC1_DCMP2 0x00000004 //< Digital Comparator 2
471 #define PWM_X_FLTSRC1_DCMP1 0x00000002 //< Digital Comparator 1
472 #define PWM_X_FLTSRC1_DCMP0 0x00000001 //< Digital Comparator 0
475 * Defines for the bit fields in the PWM_O_X_MINFLTPER register.
477 #define PWM_X_MINFLTPER_M 0x0000FFFF //< Minimum Fault Period
478 #define PWM_X_MINFLTPER_S 0
481 * Defines for the bit fields in the PWM_O_X_FLTSEN register.
483 #define PWM_X_FLTSEN_FAULT3 0x00000008 //< Fault3 Sense
484 #define PWM_X_FLTSEN_FAULT2 0x00000004 //< Fault2 Sense
485 #define PWM_X_FLTSEN_FAULT1 0x00000002 //< Fault1 Sense
486 #define PWM_X_FLTSEN_FAULT0 0x00000001 //< Fault0 Sense
489 * Defines for the bit fields in the PWM_O_X_FLTSTAT0 register.
491 #define PWM_X_FLTSTAT0_FAULT3 0x00000008 //< Fault Input 3
492 #define PWM_X_FLTSTAT0_FAULT2 0x00000004 //< Fault Input 2
493 #define PWM_X_FLTSTAT0_FAULT1 0x00000002 //< Fault Input 1
494 #define PWM_X_FLTSTAT0_FAULT0 0x00000001 //< Fault Input 0
497 * Defines for the bit fields in the PWM_O_X_FLTSTAT1 register.
499 #define PWM_X_FLTSTAT1_DCMP7 0x00000080 //< Digital Comparator 7 Trigger
500 #define PWM_X_FLTSTAT1_DCMP6 0x00000040 //< Digital Comparator 6 Trigger
501 #define PWM_X_FLTSTAT1_DCMP5 0x00000020 //< Digital Comparator 5 Trigger
502 #define PWM_X_FLTSTAT1_DCMP4 0x00000010 //< Digital Comparator 4 Trigger
503 #define PWM_X_FLTSTAT1_DCMP3 0x00000008 //< Digital Comparator 3 Trigger
504 #define PWM_X_FLTSTAT1_DCMP2 0x00000004 //< Digital Comparator 2 Trigger
505 #define PWM_X_FLTSTAT1_DCMP1 0x00000002 //< Digital Comparator 1 Trigger
506 #define PWM_X_FLTSTAT1_DCMP0 0x00000001 //< Digital Comparator 0 Trigger
509 * Defines for the PWM Generator standard offsets.
511 #define PWM_O_X_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Gen Control Reg
512 #define PWM_O_X_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Gen Int/Trig Enable Reg
513 #define PWM_O_X_RIS (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Gen Raw Int Status Reg
514 #define PWM_O_X_ISC (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< Gen Int Status Reg
515 #define PWM_O_X_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< Gen Load Reg
516 #define PWM_O_X_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< Gen Counter Reg
517 #define PWM_O_X_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< Gen Compare A Reg
518 #define PWM_O_X_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< Gen Compare B Reg
519 #define PWM_O_X_GENA (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< Gen Generator A Ctrl Reg
520 #define PWM_O_X_GENB (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< Gen Generator B Ctrl Reg
521 #define PWM_O_X_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< Gen Dead Band Ctrl Reg
522 #define PWM_O_X_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000002C))) //< Gen DB Rising Edge Delay Reg
523 #define PWM_O_X_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000030))) //< Gen DB Falling Edge Delay Reg
524 #define PWM_O_X_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000034))) //< Fault pin, comparator condition
525 #define PWM_O_X_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000038))) //< Digital comparator condition
526 #define PWM_O_X_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000003C))) //< Fault minimum period extension
527 #define PWM_GEN_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 base
528 #define PWM_GEN_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 base
529 #define PWM_GEN_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 base
530 #define PWM_GEN_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 base
533 * Defines for the PWM Generator extended offsets.
535 #define PWM_O_X_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Fault logic sense
536 #define PWM_O_X_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Pin and comparator status
537 #define PWM_O_X_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Digital comparator status
538 #define PWM_EXT_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 extended base
539 #define PWM_EXT_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 extended base
540 #define PWM_EXT_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 extended base
541 #define PWM_EXT_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 extended base
543 #endif /* LM3S_PWM_H */