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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief CHIP ID SAM3 definitions.
40 * CHIP ID base registers addresses.
42 #define CHIPID_CIDR (*((reg32_t *)(0x400E0940)))
44 #define CHIPID_VERSION_MASK 0x1F
45 #define CHIPID_VERSION() ((CHIPID_CIDR) & CHIPID_VERSION_MASK) ///< Current version of the device.
47 #define CHIPID_EPRCOC_SHIFT 5
48 #define CHIPID_EPRCOC_MASK 0xE0
49 #define CHIPID_EPRCOC() (((CHIPID_CIDR) & CHIPID_EPRCOC_MASK) >> CHIPID_EPRCOC_SHIFT) ///< Embedded processor.
51 #define CHIPID_NVPSIZ_SHIFT 8
52 #define CHIPID_NVPSIZ_MASK 0xF00 ///< Nonvolatile program memory size.
53 #define CHIPID_NVPSIZ() (((CHIPID_CIDR) & CHIPID_NVPSIZ_MASK) >> CHIPID_NVPSIZ_SHIFT) ///< Nonvolatile program memory size.
55 #define CHIPID_NVPSIZ2_SHIFT 12
56 #define CHIPID_NVPSIZ2_MASK 0xF000 ///< Second nonvolatile program memory size.
57 #define CHIPID_NVPSIZ2() (((CHIPID_CIDR) & CHIPID_NVPSIZ2_MASK) >> CHIPID_NVPSIZ2_SHIFT) ///< Second nonvolatile program memory size.
59 #define CHIPID_SRAMSIZ_SHIFT 16
60 #define CHIPID_SRAMSIZ_MASK 0xF0000 ///< Internal SRAM size.
61 #define CHIPID_SRAMSIZ() (((CHIPID_CIDR) & CHIPID_SRAMSIZ_MASK) >> CHIPID_SRAMSIZ_SHIFT) ///< Internal SRAM size.
63 #define CHIPID_ARCH_SHIFT 20
64 #define CHIPID_ARCH_MASK 0xFF00000 ///< Architecture identifier.
65 #define CHIPID_ARCH() (((CHIPID_CIDR) & CHIPID_ARCH_MASK) >> CHIPID_ARCH_SHIFT) ///< Architecture identifier.
67 #define CHIPID_NVTYP_SHIFT 28
68 #define CHIPID_NVTYP_MASK 0x70000000 ///< Nonvolatile program memory type.
69 #define CHIPID_NVTYP() (((CHIPID_CIDR) & CHIPID_NVTYP_MASK) >> CHIPID_NVTYP_SHIFT) ///< Nonvolatile program memory type.
72 const char *chipid_eproc_name(int idx);
73 const char *chipid_nvpsize(int idx);
74 const char *chipid_sramsize(int idx);
75 const char *chipid_archnames(unsigned value);
76 const char *chipid_nvptype(int idx);
78 #endif /* SAM3_CHIPID_H */