4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/
33 * \author Daniele Basile <asterix@develer.com>
35 * SAM3 Digital to Analog to Converter.
44 /** DACC registers base. */
45 #define DACC_BASE 0x400C8000
48 * DACC control register
51 #define DACC_CR_OFF 0x00000000 ///< Control register offeset.
52 #define DACC_CR (*((reg32_t*)(DACC_BASE + DACC_CR_OFF))) ///< Control register address.
53 #define DACC_SWRST 0 ///< Software reset.
60 #define DACC_MR_OFF 0x00000004 ///< Mode register offeset.
61 #define DACC_MR (*((reg32_t*) (DACC_BASE + DACC_MR_OFF))) ///< Mode register address.
62 #define DACC_TRGEN 0 ///< Trigger enable.
63 #define DACC_TRGSEL_MASK 0x14 ///< Trigger selection mask.
64 #define DACC_TRGSEL_SHIFT 1 ///< Trigger selection shift.
65 #define DACC_WORD 4 ///< Word transfer.
66 #define DACC_SLEEP 5 ///< Sleep mode.Fast Wake up Mode
67 #define DACC_FASTWKUP 6 ///< Fast Wake up Mode
68 #define DACC_REFRESH_MASK 0xFF00 ///< Refresh Period mask
69 #define DACC_REFRESH_SHIFT 8 ///< Refresh Period shift
70 #define DACC_USER_SEL_MASK 0x30000 ///< User Channel Selection mask
71 #define DACC_USER_SEL_SHIFT 16 ///< User Channel Selection shift
72 #define DACC_TAG 20 ///< Tag selection mode
73 #define DACC_MAXS 21 ///< Max speed mode
74 #define DACC_STARTUP_MASK 0x3F000000 ///< Startup time selection
75 #define DACC_STARTUP_SHIFT 24 ///< Startup time selsection shift
80 * $WIZ$ sam3x_dac_tc = "DACC_TRGSEL_TIO_CH0", "DACC_TRGSEL_TIO_CH1", "DACC_TRGSEL_TIO_CH2", "DACC_TRGSEL_PWM0", "DACC_TRGSEL_PWM1"
83 #define DACC_TRGSEL_TIO_CH0 1
84 #define DACC_TRGSEL_TIO_CH1 2
85 #define DACC_TRGSEL_TIO_CH2 3
86 #define DACC_TRGSEL_PWM0 4
87 #define DACC_TRGSEL_PWM1 5
90 #define DACC_MR_STARTUP_0 0 ///< 0 periods of DACClock
91 #define DACC_MR_STARTUP_8 1 ///< 8 periods of DACClock
92 #define DACC_MR_STARTUP_16 2 ///< 16 periods of of DACClock
93 #define DACC_MR_STARTUP_24 3 ///< 24 periods of of DACClock
94 #define DACC_MR_STARTUP_64 4 ///< 64 periods of of DACClock
95 #define DACC_MR_STARTUP_80 5 ///< 70 periods of of DACClock
96 #define DACC_MR_STARTUP_96 6 ///< 96 periods of of DACClock
97 #define DACC_MR_STARTUP_112 7 ///< 112 periods of of DACClock
98 #define DACC_MR_STARTUP_512 8 ///< 512 periods of DACClock
99 #define DACC_MR_STARTUP_576 9 ///< 576 periods of DACClock
100 #define DACC_MR_STARTUP_640 10 ///< 640 periods of DACClock
101 #define DACC_MR_STARTUP_704 11 ///< 704 periods of DACClock
102 #define DACC_MR_STARTUP_768 12 ///< 768 periods of DACClock
103 #define DACC_MR_STARTUP_832 13 ///< 832 periods of DACClock
104 #define DACC_MR_STARTUP_896 14 ///< 896 periods of DACClock
105 #define DACC_MR_STARTUP_960 15 ///< 960 periods of DACClock
106 #define DACC_MR_STARTUP_1024 16 ///< 1024 periods of DACClock
107 #define DACC_MR_STARTUP_1088 17 ///< 1088 periods of DACClock
108 #define DACC_MR_STARTUP_1152 18 ///< 1152 periods of DACClock
109 #define DACC_MR_STARTUP_1216 19 ///< 1216 periods of DACClock
110 #define DACC_MR_STARTUP_1280 20 ///< 1280 periods of DACClock
111 #define DACC_MR_STARTUP_1344 21 ///< 1344 periods of DACClock
112 #define DACC_MR_STARTUP_1408 22 ///< 1408 periods of DACClock
113 #define DACC_MR_STARTUP_1472 23 ///< 1472 periods of DACClock
114 #define DACC_MR_STARTUP_1536 24 ///< 1536 periods of DACClock
115 #define DACC_MR_STARTUP_1600 25 ///< 1600 periods of DACClock
116 #define DACC_MR_STARTUP_1664 26 ///< 1664 periods of DACClock
117 #define DACC_MR_STARTUP_1728 27 ///< 1728 periods of DACClock
118 #define DACC_MR_STARTUP_1792 28 ///< 1792 periods of DACClock
119 #define DACC_MR_STARTUP_1856 29 ///< 1856 periods of DACClock
120 #define DACC_MR_STARTUP_1920 30 ///< 1920 periods of DACClock
121 #define DACC_MR_STARTUP_1984 31 ///< 1984 periods of DACClock
125 * DACC channel enable register
127 #define DACC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
128 #define DACC_CHER (*((reg32_t*) (DACC_BASE + DACC_CHER_OFF))) ///< Channel enable register address.
131 * DACC channel disable register
133 #define DACC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
134 #define DACC_CHDR (*((reg32_t*) (DACC_BASE + DACC_CHDR_OFF))) ///< Channel disable register address.
137 * DACC channel status register
139 #define DACC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
140 #define DACC_CHSR (*((reg32_t*) (DACC_BASE + DACC_CHSR_OFF))) ///< Channel status register address.
142 #define DACC_CH0 0 ///< Channel 0.
143 #define DACC_CH1 1 ///< Channel 1.
147 * DACC Conversion data register
149 #define DACC_CDR_OFF 0x00000020 ///< Conversion data register offeset.
150 #define DACC_CDR (*((reg32_t*) (DACC_BASE + DACC_CDR_OFF))) ///< Conversion data register address.
154 * DACC Interrupt enable register
156 #define DACC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
157 #define DACC_IER (*((reg32_t*) (DACC_BASE + DACC_IER_OFF))) ///< Interrupt enable register address.
160 * DACC Interrupt disable register
162 #define DACC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
163 #define DACC_IDR (*((reg32_t*) (DACC_BASE + DACC_IDR_OFF))) ///< Interrupt disable register address.
166 * DACC Interrupt disable register
168 #define DACC_IMR_OFF 0x0000002C ///< Interrupt disable register offeset.
169 #define DACC_IMR (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF))) ///< Interrupt disable register address.
172 * DACC Interrupt status register
174 #define DACC_ISR_OFF 0x00000030 ///< Interrupt disable status offeset.
175 #define DACC_ISR (*((reg32_t*) (DACC_BASE + DACC_ISR_OFF))) ///< Interrupt status register address.
177 #define DACC_TXRDY 0 ///< Transmit ready interrupt
178 #define DACC_EOC 1 ///< End of conversion interrupt
179 #define DACC_ENDTX 2 ///< End of transmit buffer interrupt
180 #define DACC_TXBUFE 3 ///< Transmit buffer empty interrupt
184 * DMA controller for DACC
187 #define DACC_RPR_OFF 0x100 ///< Receive Pointer Register.
188 #define DACC_RPR (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF))) ///< Receive Pointer Register.
190 #define DACC_RCR_OFF 0x104 ///< Receive Counter Register.
191 #define DACC_RCR (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF))) ///< Receive Counter Register.
193 #define DACC_TPR_OFF 0x108 ///< Transmit Pointer Register.
194 #define DACC_TPR (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF))) ///< Transmit Pointer Register.
196 #define DACC_TCR_OFF 0x10C ///< Transmit Counter Register.
197 #define DACC_TCR (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF))) ///< Transmit Counter Register.
199 #define DACC_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
200 #define DACC_RNPR (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF))) ///< Receive Next Pointer Register.
202 #define DACC_RNCR_OFF 0x114 ///< Receive Next Counter Register.
203 #define DACC_RNCR (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF))) ///< Receive Next Counter Register.
205 #define DACC_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
206 #define DACC_TNPR (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF))) ///< Transmit Next Pointer Register.
208 #define DACC_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
209 #define DACC_TNCR (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF))) ///< Transmit Next Counter Register.
211 #define DACC_PTCR_OFF 0x120 ///< Transfer Control Register.
212 #define DACC_PTCR (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF))) ///< Transfer Control Register.
214 #define DACC_PTSR_OFF 0x124 ///< Transfer Status Register.
215 #define DACC_PTSR (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF))) ///< Transfer Status Register.
218 #define DACC_PTCR_RXTEN 0 ///< DACC_PTCR Receiver Transfer Enable.
219 #define DACC_PTCR_RXTDIS 1 ///< DACC_PTCR Receiver Transfer Disable.
220 #define DACC_PTCR_TXTEN 8 ///< DACC_PTCR Transmitter Transfer Enable.
221 #define DACC_PTCR_TXTDIS 9 ///< DACC_PTCR Transmitter Transfer Disable.
222 #define DACC_PTSR_RXTEN 0 ///< DACC_PTSR Receiver Transfer Enable.
223 #define DACC_PTSR_TXTEN 8 ///< DACC_PTSR Transmitter Transfer Enable.
225 #endif /* SAM3_DACC_H */