4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Atmel SAM3 enhanced embedded flash controller definitions.
40 * EEFC base registers addresses.
43 #define EEFC0_BASE 0x400E0A00
45 #define EEFC1_BASE 0x400E0C00
51 * EFC register offsets.
54 #define EEFC_FMR_OFF 0x0 ///< Flash Mode Register
55 #define EEFC_FCR_OFF 0x4 ///< Flash Command Register
56 #define EEFC_FSR_OFF 0x8 ///< Flash Status Register
57 #define EEFC_FRR_OFF 0xC ///< Flash Result Register
64 #define EEFC0_FMR (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
65 #define EEFC0_FCR (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
66 #define EEFC0_FSR (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
67 #define EEFC0_FRR (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
70 #define EEFC1_FMR (*((reg32_t *)(EEFC1_BASE + EEFC_FMR_OFF))) ///< Flash Mode Register
71 #define EEFC1_FCR (*((reg32_t *)(EEFC1_BASE + EEFC_FCR_OFF))) ///< Flash Command Register
72 #define EEFC1_FSR (*((reg32_t *)(EEFC1_BASE + EEFC_FSR_OFF))) ///< Flash Status Register
73 #define EEFC1_FRR (*((reg32_t *)(EEFC1_BASE + EEFC_FRR_OFF))) ///< Flash Result Register
80 * Defines for bit fields in EEFC_FMR register.
83 #define EEFC_FMR_FRDY 0 ///< Ready Interrupt Enable
84 #define EEFC_FMR_FWS_SHIFT 8
85 #define EEFC_FMR_FWS_MASK (0xf << EEFC_FMR_FWS_SHIFT) ///< Flash Wait State
86 #define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_MASK & ((value) << EEFC_FMR_FWS_SHIFT))
87 #define EEFC_FMR_FAM 24 ///< Flash Access Mode
91 * Defines for bit fields in EEFC_FCR register.
94 #define EEFC_FCR_FCMD_MASK 0xff ///< Flash Command
95 #define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_MASK & (value))
96 #define EEFC_FCR_FARG_SHIFT 8
97 #define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) ///< Flash Command Argument
98 #define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT))
99 #define EEFC_FCR_FKEY_SHIFT 24
100 #define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT) ///< Flash Writing Protection Key
101 #define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_MASK & ((value) << EEFC_FCR_FKEY_SHIFT))
105 * Defines for bit fields in EEFC_FSR register.
108 #define EEFC_FSR_FRDY 0 ///< Flash Ready Status
109 #define EEFC_FSR_FCMDE 1 ///< Flash Command Error Status
110 #define EEFC_FSR_FLOCKE 2 ///< Flash Lock Error Status
113 #endif /* SAM3_FLASH_H */