4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007,2010 Develer S.r.l. (http://www.develer.com/)
34 * \author Francesco Sacchi <batt@develer.com>
36 * Atmel SAM3 Parallel input/output controller.
37 * This file is based on NUT/OS implementation. See license below.
41 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
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51 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of the copyright holders nor the names of
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
66 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * For additional information see http://www.ethernut.de/
76 * PIO registers base addresses.
79 #define PIOA_BASE 0x400E0E00
80 #define PIOB_BASE 0x400E1000
81 #define PIOC_BASE 0x400E1200
84 #define PIOD_BASE 0x400E1400
85 #define PIOE_BASE 0x400E1600
86 #define PIOF_BASE 0x400E1800
90 /** PIO Register Offsets */
92 #define PIO_PER_OFF 0x00000000 ///< PIO enable register offset.
93 #define PIO_PDR_OFF 0x00000004 ///< PIO disable register offset.
94 #define PIO_PSR_OFF 0x00000008 ///< PIO status register offset.
95 #define PIO_OER_OFF 0x00000010 ///< Output enable register offset.
96 #define PIO_ODR_OFF 0x00000014 ///< Output disable register offset.
97 #define PIO_OSR_OFF 0x00000018 ///< Output status register offset.
98 #define PIO_IFER_OFF 0x00000020 ///< Input filter enable register offset.
99 #define PIO_IFDR_OFF 0x00000024 ///< Input filter disable register offset.
100 #define PIO_IFSR_OFF 0x00000028 ///< Input filter status register offset.
101 #define PIO_SODR_OFF 0x00000030 ///< Set output data register offset.
102 #define PIO_CODR_OFF 0x00000034 ///< Clear output data register offset.
103 #define PIO_ODSR_OFF 0x00000038 ///< Output data status register offset.
104 #define PIO_PDSR_OFF 0x0000003C ///< Pin data status register offset.
105 #define PIO_IER_OFF 0x00000040 ///< Interrupt enable register offset.
106 #define PIO_IDR_OFF 0x00000044 ///< Interrupt disable register offset.
107 #define PIO_IMR_OFF 0x00000048 ///< Interrupt mask register offset.
108 #define PIO_ISR_OFF 0x0000004C ///< Interrupt status register offset.
109 #define PIO_MDER_OFF 0x00000050 ///< Multi-driver enable register offset.
110 #define PIO_MDDR_OFF 0x00000054 ///< Multi-driver disable register offset.
111 #define PIO_MDSR_OFF 0x00000058 ///< Multi-driver status register offset.
112 #define PIO_PUDR_OFF 0x00000060 ///< Pull-up disable register offset.
113 #define PIO_PUER_OFF 0x00000064 ///< Pull-up enable register offset.
114 #define PIO_PUSR_OFF 0x00000068 ///< Pull-up status register offset.
115 #if CPU_CM3_SAM3X || CPU_CM3_SAM3U
116 #define PIO_ABSR_OFF 0x00000070 ///< PIO peripheral select register offset.
117 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
118 #define PIO_ABCDSR1_OFF 0x00000070 ///< PIO peripheral select register 1 offset.
119 #define PIO_ABCDSR2_OFF 0x00000074 ///< PIO peripheral select register 2 offset.
121 #error Undefined PIO peripheral select register for selected cpu
123 #define PIO_OWER_OFF 0x000000A0 ///< PIO output write enable register offset.
124 #define PIO_OWDR_OFF 0x000000A4 ///< PIO output write disable register offset.
125 #define PIO_OWSR_OFF 0x000000A8 ///< PIO output write status register offset.
129 #if defined(PIOA_BASE)
130 /** PIO A Register Addresses */
132 #define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset))))
134 #define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
135 #define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
136 #define PIOA_PSR PIOA_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
137 #define PIOA_OER PIOA_ACCESS(PIO_OER_OFF) ///< Output enable register address.
138 #define PIOA_ODR PIOA_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
139 #define PIOA_OSR PIOA_ACCESS(PIO_OSR_OFF) ///< Output status register address.
140 #define PIOA_IFER PIOA_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
141 #define PIOA_IFDR PIOA_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
142 #define PIOA_IFSR PIOA_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
143 #define PIOA_SODR PIOA_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
144 #define PIOA_CODR PIOA_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
145 #define PIOA_ODSR PIOA_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
146 #define PIOA_PDSR PIOA_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
147 #define PIOA_IER PIOA_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
148 #define PIOA_IDR PIOA_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
149 #define PIOA_IMR PIOA_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
150 #define PIOA_ISR PIOA_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
151 #define PIOA_MDER PIOA_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
152 #define PIOA_MDDR PIOA_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
153 #define PIOA_MDSR PIOA_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
154 #define PIOA_PUDR PIOA_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
155 #define PIOA_PUER PIOA_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
156 #define PIOA_PUSR PIOA_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
158 #define PIOA_ABSR PIOA_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
160 #define PIOA_ABCDSR1 PIOA_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
161 #define PIOA_ABCDSR2 PIOA_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
163 #define PIOA_OWER PIOA_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
164 #define PIOA_OWDR PIOA_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
165 #define PIOA_OWSR PIOA_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
167 #endif /* PIOA_BASE */
169 #if defined(PIOB_BASE)
170 /** PIO B Register Addresses */
172 #define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset))))
174 #define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
175 #define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
176 #define PIOB_PSR PIOB_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
177 #define PIOB_OER PIOB_ACCESS(PIO_OER_OFF) ///< Output enable register address.
178 #define PIOB_ODR PIOB_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
179 #define PIOB_OSR PIOB_ACCESS(PIO_OSR_OFF) ///< Output status register address.
180 #define PIOB_IFER PIOB_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
181 #define PIOB_IFDR PIOB_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
182 #define PIOB_IFSR PIOB_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
183 #define PIOB_SODR PIOB_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
184 #define PIOB_CODR PIOB_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
185 #define PIOB_ODSR PIOB_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
186 #define PIOB_PDSR PIOB_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
187 #define PIOB_IER PIOB_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
188 #define PIOB_IDR PIOB_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
189 #define PIOB_IMR PIOB_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
190 #define PIOB_ISR PIOB_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
191 #define PIOB_MDER PIOB_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
192 #define PIOB_MDDR PIOB_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
193 #define PIOB_MDSR PIOB_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
194 #define PIOB_PUDR PIOB_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
195 #define PIOB_PUER PIOB_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
196 #define PIOB_PUSR PIOB_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
198 #define PIOB_ABSR PIOB_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
200 #define PIOB_ABCDSR1 PIOB_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
201 #define PIOB_ABCDSR2 PIOB_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
203 #define PIOB_OWER PIOB_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
204 #define PIOB_OWDR PIOB_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
205 #define PIOB_OWSR PIOB_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
207 #endif /* PIOB_BASE */
209 #if defined(PIOC_BASE)
210 /** PIO C Register Addresses */
212 #define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset))))
214 #define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
215 #define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
216 #define PIOC_PSR PIOC_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
217 #define PIOC_OER PIOC_ACCESS(PIO_OER_OFF) ///< Output enable register address.
218 #define PIOC_ODR PIOC_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
219 #define PIOC_OSR PIOC_ACCESS(PIO_OSR_OFF) ///< Output status register address.
220 #define PIOC_IFER PIOC_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
221 #define PIOC_IFDR PIOC_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
222 #define PIOC_IFSR PIOC_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
223 #define PIOC_SODR PIOC_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
224 #define PIOC_CODR PIOC_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
225 #define PIOC_ODSR PIOC_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
226 #define PIOC_PDSR PIOC_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
227 #define PIOC_IER PIOC_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
228 #define PIOC_IDR PIOC_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
229 #define PIOC_IMR PIOC_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
230 #define PIOC_ISR PIOC_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
231 #define PIOC_MDER PIOC_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
232 #define PIOC_MDDR PIOC_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
233 #define PIOC_MDSR PIOC_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
234 #define PIOC_PUDR PIOC_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
235 #define PIOC_PUER PIOC_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
236 #define PIOC_PUSR PIOC_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
238 #define PIOC_ABSR PIOC_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
240 #define PIOC_ABCDSR1 PIOC_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
241 #define PIOC_ABCDSR2 PIOC_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
243 #define PIOC_OWER PIOC_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
244 #define PIOC_OWDR PIOC_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
245 #define PIOC_OWSR PIOC_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
247 #endif /* PIOC_BASE */
249 #if defined(PIOD_BASE)
250 /** PIO C Register Addresses */
252 #define PIOD_ACCESS(offset) (*((reg32_t *)(PIOD_BASE + (offset))))
254 #define PIOD_PER PIOD_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
255 #define PIOD_PDR PIOD_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
256 #define PIOD_PSR PIOD_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
257 #define PIOD_OER PIOD_ACCESS(PIO_OER_OFF) ///< Output enable register address.
258 #define PIOD_ODR PIOD_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
259 #define PIOD_OSR PIOD_ACCESS(PIO_OSR_OFF) ///< Output status register address.
260 #define PIOD_IFER PIOD_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
261 #define PIOD_IFDR PIOD_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
262 #define PIOD_IFSR PIOD_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
263 #define PIOD_SODR PIOD_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
264 #define PIOD_CODR PIOD_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
265 #define PIOD_ODSR PIOD_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
266 #define PIOD_PDSR PIOD_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
267 #define PIOD_IER PIOD_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
268 #define PIOD_IDR PIOD_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
269 #define PIOD_IMR PIOD_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
270 #define PIOD_ISR PIOD_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
271 #define PIOD_MDER PIOD_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
272 #define PIOD_MDDR PIOD_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
273 #define PIOD_MDSR PIOD_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
274 #define PIOD_PUDR PIOD_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
275 #define PIOD_PUER PIOD_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
276 #define PIOD_PUSR PIOD_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
278 #define PIOD_ABSR PIOD_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
280 #define PIOD_ABCDSR1 PIOD_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
281 #define PIOD_ABCDSR2 PIOD_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
283 #define PIOD_OWER PIOD_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
284 #define PIOD_OWDR PIOD_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
285 #define PIOD_OWSR PIOD_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
287 #endif /* PIOD_BASE */
289 #if defined(PIOE_BASE)
290 /** PIO C Register Addresses */
292 #define PIOE_ACCESS(offset) (*((reg32_t *)(PIOE_BASE + (offset))))
294 #define PIOE_PER PIOE_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
295 #define PIOE_PDR PIOE_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
296 #define PIOE_PSR PIOE_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
297 #define PIOE_OER PIOE_ACCESS(PIO_OER_OFF) ///< Output enable register address.
298 #define PIOE_ODR PIOE_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
299 #define PIOE_OSR PIOE_ACCESS(PIO_OSR_OFF) ///< Output status register address.
300 #define PIOE_IFER PIOE_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
301 #define PIOE_IFDR PIOE_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
302 #define PIOE_IFSR PIOE_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
303 #define PIOE_SODR PIOE_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
304 #define PIOE_CODR PIOE_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
305 #define PIOE_ODSR PIOE_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
306 #define PIOE_PDSR PIOE_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
307 #define PIOE_IER PIOE_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
308 #define PIOE_IDR PIOE_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
309 #define PIOE_IMR PIOE_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
310 #define PIOE_ISR PIOE_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
311 #define PIOE_MDER PIOE_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
312 #define PIOE_MDDR PIOE_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
313 #define PIOE_MDSR PIOE_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
314 #define PIOE_PUDR PIOE_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
315 #define PIOE_PUER PIOE_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
316 #define PIOE_PUSR PIOE_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
318 #define PIOE_ABSR PIOE_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
320 #define PIOE_ABCDSR1 PIOE_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
321 #define PIOE_ABCDSR2 PIOE_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
323 #define PIOE_OWER PIOE_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
324 #define PIOE_OWDR PIOE_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
325 #define PIOE_OWSR PIOE_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
327 #endif /* PIOE_BASE */
329 #if defined(PIOF_BASE)
330 /** PIO C Register Addresses */
332 #define PIOF_ACCESS(offset) (*((reg32_t *)(PIOF_BASE + (offset))))
334 #define PIOF_PER PIOF_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
335 #define PIOF_PDR PIOF_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
336 #define PIOF_PSR PIOF_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
337 #define PIOF_OER PIOF_ACCESS(PIO_OER_OFF) ///< Output enable register address.
338 #define PIOF_ODR PIOF_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
339 #define PIOF_OSR PIOF_ACCESS(PIO_OSR_OFF) ///< Output status register address.
340 #define PIOF_IFER PIOF_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
341 #define PIOF_IFDR PIOF_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
342 #define PIOF_IFSR PIOF_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
343 #define PIOF_SODR PIOF_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
344 #define PIOF_CODR PIOF_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
345 #define PIOF_ODSR PIOF_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
346 #define PIOF_PDSR PIOF_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
347 #define PIOF_IER PIOF_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
348 #define PIOF_IDR PIOF_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
349 #define PIOF_IMR PIOF_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
350 #define PIOF_ISR PIOF_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
351 #define PIOF_MDER PIOF_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
352 #define PIOF_MDDR PIOF_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
353 #define PIOF_MDSR PIOF_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
354 #define PIOF_PUDR PIOF_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
355 #define PIOF_PUER PIOF_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
356 #define PIOF_PUSR PIOF_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
358 #define PIOF_ABSR PIOF_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral select register address.
360 #define PIOF_ABCDSR1 PIOF_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
361 #define PIOF_ABCDSR2 PIOF_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
363 #define PIOF_OWER PIOF_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
364 #define PIOF_OWDR PIOF_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
365 #define PIOF_OWSR PIOF_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
367 #endif /* PIOF_BASE */
370 #define PIO_PERIPH_A 0
371 #define PIO_PERIPH_B 1
372 #ifdef PIO_ABCDSR1_OFF
373 #define PIO_PERIPH_C 2
374 #define PIO_PERIPH_D 3
378 * Set peripheral on I/O ports.
380 * \param base PIO port base
381 * \param mask mask of I/O pin to manipulate
382 * \param function function to assign to selected pins (PIO_PERIPH_A, B, ...)
384 #ifdef PIO_ABCDSR1_OFF
385 #define PIO_PERIPH_SEL(base, mask, function) do { \
386 HWREG((base) + PIO_ABCDSR1_OFF) &= ~(mask); \
387 HWREG((base) + PIO_ABCDSR2_OFF) &= ~(mask); \
388 if ((function) & 1) \
389 HWREG((base) + PIO_ABCDSR1_OFF) |= (mask); \
390 if ((function) & 2) \
391 HWREG((base) + PIO_ABCDSR2_OFF) |= (mask); \
394 #define PIO_PERIPH_SEL(base, mask, function) do { \
395 HWREG((base) + PIO_ABSR_OFF) &= ~(mask); \
396 if ((function) & 1) \
397 HWREG((base) + PIO_ABSR_OFF) |= (mask); \
402 #endif /* SAM3_PIO_H */