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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3X/A/U Static Memory Controller definitions.
40 * SMC registers defined only for SAM3X/A and U for now
42 #if CPU_CM3_SAM3X || CPU_CM3_SAM3U
44 /** SMC registers base. */
45 #define SMC_BASE 0x400E0000
49 * SMC register offsets.
52 #define SMC_CFG_OFF 0x000 ///< NFC Configuration
53 #define SMC_CTRL_OFF 0x004 ///< NFC Control
54 #define SMC_SR_OFF 0x008 ///< NFC Status
55 #define SMC_IER_OFF 0x00C ///< NFC Interrupt Enable
56 #define SMC_IDR_OFF 0x010 ///< NFC Interrupt Disable
57 #define SMC_IMR_OFF 0x014 ///< NFC Interrupt Mask
58 #define SMC_ADDR_OFF 0x018 ///< NFC Address Cycle Zero
59 #define SMC_BANK_OFF 0x01C ///< Bank Address
60 #define SMC_ECC_CTRL_OFF 0x020 ///< ECC Control
61 #define SMC_ECC_MD_OFF 0x024 ///< ECC Mode
62 #define SMC_ECC_SR1_OFF 0x028 ///< ECC Status 1
63 #define SMC_ECC_PR0_OFF 0x02C ///< ECC Parity 0
64 #define SMC_ECC_PR1_OFF 0x030 ///< ECC parity 1
65 #define SMC_ECC_SR2_OFF 0x034 ///< ECC status 2
66 #define SMC_ECC_PR2_OFF 0x038 ///< ECC parity 2
67 #define SMC_ECC_PR3_OFF 0x03C ///< ECC parity 3
68 #define SMC_ECC_PR4_OFF 0x040 ///< ECC parity 4
69 #define SMC_ECC_PR5_OFF 0x044 ///< ECC parity 5
70 #define SMC_ECC_PR6_OFF 0x048 ///< ECC parity 6
71 #define SMC_ECC_PR7_OFF 0x04C ///< ECC parity 7
72 #define SMC_ECC_PR8_OFF 0x050 ///< ECC parity 8
73 #define SMC_ECC_PR9_OFF 0x054 ///< ECC parity 9
74 #define SMC_ECC_PR10_OFF 0x058 ///< ECC parity 10
75 #define SMC_ECC_PR11_OFF 0x05C ///< ECC parity 11
76 #define SMC_ECC_PR12_OFF 0x060 ///< ECC parity 12
77 #define SMC_ECC_PR13_OFF 0x064 ///< ECC parity 13
78 #define SMC_ECC_PR14_OFF 0x068 ///< ECC parity 14
79 #define SMC_ECC_PR15_OFF 0x06C ///< ECC parity 15
80 #define SMC_SETUP0_OFF 0x070 ///< SETUP (CS_number = 0)
81 #define SMC_PULSE0_OFF 0x074 ///< PULSE (CS_number = 0)
82 #define SMC_CYCLE0_OFF 0x078 ///< CYCLE (CS_number = 0)
83 #define SMC_TIMINGS0_OFF 0x07C ///< TIMINGS (CS_number = 0)
84 #define SMC_MODE0_OFF 0x080 ///< MODE (CS_number = 0)
85 #define SMC_SETUP1_OFF 0x084 ///< SETUP (CS_number = 1)
86 #define SMC_PULSE1_OFF 0x088 ///< PULSE (CS_number = 1)
87 #define SMC_CYCLE1_OFF 0x08C ///< CYCLE (CS_number = 1)
88 #define SMC_TIMINGS1_OFF 0x090 ///< TIMINGS (CS_number = 1)
89 #define SMC_MODE1_OFF 0x094 ///< MODE (CS_number = 1)
90 #define SMC_SETUP2_OFF 0x098 ///< SETUP (CS_number = 2)
91 #define SMC_PULSE2_OFF 0x09C ///< PULSE (CS_number = 2)
92 #define SMC_CYCLE2_OFF 0x0A0 ///< CYCLE (CS_number = 2)
93 #define SMC_TIMINGS2_OFF 0x0A4 ///< TIMINGS (CS_number = 2)
94 #define SMC_MODE2_OFF 0x0A8 ///< MODE (CS_number = 2)
95 #define SMC_SETUP3_OFF 0x0AC ///< SETUP (CS_number = 3)
96 #define SMC_PULSE3_OFF 0x0B0 ///< PULSE (CS_number = 3)
97 #define SMC_CYCLE3_OFF 0x0B4 ///< CYCLE (CS_number = 3)
98 #define SMC_TIMINGS3_OFF 0x0B8 ///< TIMINGS (CS_number = 3)
99 #define SMC_MODE3_OFF 0x0BC ///< MODE (CS_number = 3)
100 #define SMC_SETUP4_OFF 0x0C0 ///< SETUP (CS_number = 4)
101 #define SMC_PULSE4_OFF 0x0C4 ///< PULSE (CS_number = 4)
102 #define SMC_CYCLE4_OFF 0x0C8 ///< CYCLE (CS_number = 4)
103 #define SMC_TIMINGS4_OFF 0x0CC ///< TIMINGS (CS_number = 4)
104 #define SMC_MODE4_OFF 0x0D0 ///< MODE (CS_number = 4)
105 #define SMC_SETUP5_OFF 0x0D4 ///< SETUP (CS_number = 5)
106 #define SMC_PULSE5_OFF 0x0D8 ///< PULSE (CS_number = 5)
107 #define SMC_CYCLE5_OFF 0x0DC ///< CYCLE (CS_number = 5)
108 #define SMC_TIMINGS5_OFF 0x0E0 ///< TIMINGS (CS_number = 5)
109 #define SMC_MODE5_OFF 0x0E4 ///< MODE (CS_number = 5)
110 #define SMC_SETUP6_OFF 0x0E8 ///< SETUP (CS_number = 6)
111 #define SMC_PULSE6_OFF 0x0EC ///< PULSE (CS_number = 6)
112 #define SMC_CYCLE6_OFF 0x0F0 ///< CYCLE (CS_number = 6)
113 #define SMC_TIMINGS6_OFF 0x0F4 ///< TIMINGS (CS_number = 6)
114 #define SMC_MODE6_OFF 0x0F8 ///< MODE (CS_number = 6)
115 #define SMC_SETUP7_OFF 0x0FC ///< SETUP (CS_number = 7)
116 #define SMC_PULSE7_OFF 0x100 ///< PULSE (CS_number = 7)
117 #define SMC_CYCLE7_OFF 0x104 ///< CYCLE (CS_number = 7)
118 #define SMC_TIMINGS7_OFF 0x108 ///< TIMINGS (CS_number = 7)
119 #define SMC_MODE7_OFF 0x10C ///< MODE (CS_number = 7)
120 #define SMC_OCMS_OFF 0x110 ///< OCMS MODE
121 #define SMC_KEY1_OFF 0x114 ///< KEY1
122 #define SMC_KEY2_OFF 0x118 ///< KEY2
123 #define SMC_WPCR_OFF 0x1E4 ///< Write Protection Control
124 #define SMC_WPSR_OFF 0x1E8 ///< Write Protection Status
131 #define SMC_CFG (*((reg32_t *)(SMC_BASE + SMC_CFG_OFF)))
132 #define SMC_CTRL (*((reg32_t *)(SMC_BASE + SMC_CTRL_OFF)))
133 #define SMC_SR (*((reg32_t *)(SMC_BASE + SMC_SR_OFF)))
134 #define SMC_IER (*((reg32_t *)(SMC_BASE + SMC_IER_OFF)))
135 #define SMC_IDR (*((reg32_t *)(SMC_BASE + SMC_IDR_OFF)))
136 #define SMC_IMR (*((reg32_t *)(SMC_BASE + SMC_IMR_OFF)))
137 #define SMC_ADDR (*((reg32_t *)(SMC_BASE + SMC_ADDR_OFF)))
138 #define SMC_BANK (*((reg32_t *)(SMC_BASE + SMC_BANK_OFF)))
139 #define SMC_ECC_CTRL (*((reg32_t *)(SMC_BASE + SMC_ECC_CTRL_OFF)))
140 #define SMC_ECC_MD (*((reg32_t *)(SMC_BASE + SMC_ECC_MD_OFF)))
141 #define SMC_ECC_SR1 (*((reg32_t *)(SMC_BASE + SMC_ECC_SR1_OFF)))
142 #define SMC_ECC_PR0 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF)))
143 #define SMC_ECC_PR1 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR1_OFF)))
144 #define SMC_ECC_SR2 (*((reg32_t *)(SMC_BASE + SMC_ECC_SR2_OFF)))
145 #define SMC_ECC_PR2 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR2_OFF)))
146 #define SMC_ECC_PR3 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR3_OFF)))
147 #define SMC_ECC_PR4 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR4_OFF)))
148 #define SMC_ECC_PR5 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR5_OFF)))
149 #define SMC_ECC_PR6 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR6_OFF)))
150 #define SMC_ECC_PR7 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR7_OFF)))
151 #define SMC_ECC_PR8 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR8_OFF)))
152 #define SMC_ECC_PR9 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR9_OFF)))
153 #define SMC_ECC_PR10 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR10_OFF)))
154 #define SMC_ECC_PR11 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR11_OFF)))
155 #define SMC_ECC_PR12 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR12_OFF)))
156 #define SMC_ECC_PR13 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR13_OFF)))
157 #define SMC_ECC_PR14 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR14_OFF)))
158 #define SMC_ECC_PR15 (*((reg32_t *)(SMC_BASE + SMC_ECC_PR15_OFF)))
159 #define SMC_SETUP0 (*((reg32_t *)(SMC_BASE + SMC_SETUP0_OFF)))
160 #define SMC_PULSE0 (*((reg32_t *)(SMC_BASE + SMC_PULSE0_OFF)))
161 #define SMC_CYCLE0 (*((reg32_t *)(SMC_BASE + SMC_CYCLE0_OFF)))
162 #define SMC_TIMINGS0 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS0_OFF)))
163 #define SMC_MODE0 (*((reg32_t *)(SMC_BASE + SMC_MODE0_OFF)))
164 #define SMC_SETUP1 (*((reg32_t *)(SMC_BASE + SMC_SETUP1_OFF)))
165 #define SMC_PULSE1 (*((reg32_t *)(SMC_BASE + SMC_PULSE1_OFF)))
166 #define SMC_CYCLE1 (*((reg32_t *)(SMC_BASE + SMC_CYCLE1_OFF)))
167 #define SMC_TIMINGS1 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS1_OFF)))
168 #define SMC_MODE1 (*((reg32_t *)(SMC_BASE + SMC_MODE1_OFF)))
169 #define SMC_SETUP2 (*((reg32_t *)(SMC_BASE + SMC_SETUP2_OFF)))
170 #define SMC_PULSE2 (*((reg32_t *)(SMC_BASE + SMC_PULSE2_OFF)))
171 #define SMC_CYCLE2 (*((reg32_t *)(SMC_BASE + SMC_CYCLE2_OFF)))
172 #define SMC_TIMINGS2 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS2_OFF)))
173 #define SMC_MODE2 (*((reg32_t *)(SMC_BASE + SMC_MODE2_OFF)))
174 #define SMC_SETUP3 (*((reg32_t *)(SMC_BASE + SMC_SETUP3_OFF)))
175 #define SMC_PULSE3 (*((reg32_t *)(SMC_BASE + SMC_PULSE3_OFF)))
176 #define SMC_CYCLE3 (*((reg32_t *)(SMC_BASE + SMC_CYCLE3_OFF)))
177 #define SMC_TIMINGS3 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS3_OFF)))
178 #define SMC_MODE3 (*((reg32_t *)(SMC_BASE + SMC_MODE3_OFF)))
179 #define SMC_SETUP4 (*((reg32_t *)(SMC_BASE + SMC_SETUP4_OFF)))
180 #define SMC_PULSE4 (*((reg32_t *)(SMC_BASE + SMC_PULSE4_OFF)))
181 #define SMC_CYCLE4 (*((reg32_t *)(SMC_BASE + SMC_CYCLE4_OFF)))
182 #define SMC_TIMINGS4 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS4_OFF)))
183 #define SMC_MODE4 (*((reg32_t *)(SMC_BASE + SMC_MODE4_OFF)))
184 #define SMC_SETUP5 (*((reg32_t *)(SMC_BASE + SMC_SETUP5_OFF)))
185 #define SMC_PULSE5 (*((reg32_t *)(SMC_BASE + SMC_PULSE5_OFF)))
186 #define SMC_CYCLE5 (*((reg32_t *)(SMC_BASE + SMC_CYCLE5_OFF)))
187 #define SMC_TIMINGS5 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS5_OFF)))
188 #define SMC_MODE5 (*((reg32_t *)(SMC_BASE + SMC_MODE5_OFF)))
189 #define SMC_SETUP6 (*((reg32_t *)(SMC_BASE + SMC_SETUP6_OFF)))
190 #define SMC_PULSE6 (*((reg32_t *)(SMC_BASE + SMC_PULSE6_OFF)))
191 #define SMC_CYCLE6 (*((reg32_t *)(SMC_BASE + SMC_CYCLE6_OFF)))
192 #define SMC_TIMINGS6 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS6_OFF)))
193 #define SMC_MODE6 (*((reg32_t *)(SMC_BASE + SMC_MODE6_OFF)))
194 #define SMC_SETUP7 (*((reg32_t *)(SMC_BASE + SMC_SETUP7_OFF)))
195 #define SMC_PULSE7 (*((reg32_t *)(SMC_BASE + SMC_PULSE7_OFF)))
196 #define SMC_CYCLE7 (*((reg32_t *)(SMC_BASE + SMC_CYCLE7_OFF)))
197 #define SMC_TIMINGS7 (*((reg32_t *)(SMC_BASE + SMC_TIMINGS7_OFF)))
198 #define SMC_MODE7 (*((reg32_t *)(SMC_BASE + SMC_MODE7_OFF)))
199 #define SMC_OCMS (*((reg32_t *)(SMC_BASE + SMC_OCMS_OFF)))
200 #define SMC_KEY1 (*((reg32_t *)(SMC_BASE + SMC_KEY1_OFF)))
201 #define SMC_KEY2 (*((reg32_t *)(SMC_BASE + SMC_KEY2_OFF)))
202 #define SMC_WPCR (*((reg32_t *)(SMC_BASE + SMC_WPCR_OFF)))
203 #define SMC_WPSR (*((reg32_t *)(SMC_BASE + SMC_WPSR_OFF)))
207 * NFC control addresses.
210 #define NFC_SRAM_BASE_ADDR 0x20100000 ///< Base address of NFC SRAM
211 #define NFC_CMD_BASE_ADDR 0x60000000 ///< Base address for NFC Address Command
215 * NFC address command values.
218 #define NFC_CMD_CMD1 (0xFF << 2) ///< Command Register Value for Cycle 1
219 #define NFC_CMD_CMD2 (0xFF << 10) ///< Command Register Value for Cycle 2
220 #define NFC_CMD_VCMD2 BV(18) ///< Valid Cycle 2 Command
221 #define NFC_CMD_ACYCLE_SHIFT 19
222 #define NFC_CMD_ACYCLE_MASK (0x7 << 19) ///< Number of Address required for the current command
223 #define NFC_CMD_ACYCLE_NONE (0x0 << 19) ///< No address cycle
224 #define NFC_CMD_ACYCLE_ONE (0x1 << 19) ///< One address cycle
225 #define NFC_CMD_ACYCLE_TWO (0x2 << 19) ///< Two address cycles
226 #define NFC_CMD_ACYCLE_THREE (0x3 << 19) ///< Three address cycles
227 #define NFC_CMD_ACYCLE_FOUR (0x4 << 19) ///< Four address cycles
228 #define NFC_CMD_ACYCLE_FIVE (0x5 << 19) ///< Five address cycles
229 #define NFC_CMD_CSID_SHIFT 22 ///< Chip Select shift
230 #define NFC_CMD_CSID_MASK (0x7 << NFC_CMD_CSID_SHIFT) ///< Chip Select mask
231 #define NFC_CMD_NFCEN BV(25) ///< NFC Enable
232 #define NFC_CMD_NFCWR BV(26) ///< NFC Write Enable
233 #define NFC_CMD_NFCCMD BV(27) ///< NFC Command Enable
238 * Defines for bit fields in SMC_CFG register.
241 #define SMC_CFG_PAGESIZE_SHIFT 0
242 #define SMC_CFG_PAGESIZE_MASK (0x3 << SMC_CFG_PAGESIZE_SHIFT)
243 #define SMC_CFG_PAGESIZE_PS512_16 (0x0 << 0)
244 #define SMC_CFG_PAGESIZE_PS1024_32 (0x1 << 0)
245 #define SMC_CFG_PAGESIZE_PS2048_64 (0x2 << 0)
246 #define SMC_CFG_PAGESIZE_PS4096_128 (0x3 << 0)
247 #define SMC_CFG_WSPARE (0x1 << 8)
248 #define SMC_CFG_RSPARE (0x1 << 9)
249 #define SMC_CFG_EDGECTRL (0x1 << 12)
250 #define SMC_CFG_RBEDGE (0x1 << 13)
251 #define SMC_CFG_DTOCYC_SHIFT 16
252 #define SMC_CFG_DTOCYC_MASK (0xf << SMC_CFG_DTOCYC_SHIFT)
253 #define SMC_CFG_DTOCYC(value) (SMC_CFG_DTOCYC_MASK & ((value) << SMC_CFG_DTOCYC_SHIFT))
254 #define SMC_CFG_DTOMUL_SHIFT 20
255 #define SMC_CFG_DTOMUL_MASK (0x7 << SMC_CFG_DTOMUL_SHIFT)
256 #define SMC_CFG_DTOMUL_X1 (0x0 << 20)
257 #define SMC_CFG_DTOMUL_X16 (0x1 << 20)
258 #define SMC_CFG_DTOMUL_X128 (0x2 << 20)
259 #define SMC_CFG_DTOMUL_X256 (0x3 << 20)
260 #define SMC_CFG_DTOMUL_X1024 (0x4 << 20)
261 #define SMC_CFG_DTOMUL_X4096 (0x5 << 20)
262 #define SMC_CFG_DTOMUL_X65536 (0x6 << 20)
263 #define SMC_CFG_DTOMUL_X1048576 (0x7 << 20)
267 * Defines for bit fields in SMC_CTRL register.
270 #define SMC_CTRL_NFCEN BV(0)
271 #define SMC_CTRL_NFCDIS BV(1)
275 * Defines for bit fields in SMC_SR register.
278 #define SMC_SR_SMCSTS BV(0)
279 #define SMC_SR_RB_RISE BV(4)
280 #define SMC_SR_RB_FALL BV(5)
281 #define SMC_SR_NFCBUSY BV(8)
282 #define SMC_SR_NFCWR BV(11)
283 #define SMC_SR_NFCSID_SHIFT 12
284 #define SMC_SR_NFCSID_MASK (0x7 << SMC_SR_NFCSID_SHIFT)
285 #define SMC_SR_XFRDONE BV(16)
286 #define SMC_SR_CMDDONE BV(17)
287 #define SMC_SR_DTOE BV(20)
288 #define SMC_SR_UNDEF BV(21)
289 #define SMC_SR_AWB BV(22)
290 #define SMC_SR_NFCASE BV(23)
291 #define SMC_SR_RB_EDGE0 BV(24)
295 * Defines for bit fields in SMC_ECC_CTRL register
298 #define SMC_ECC_CTRL_RST BV(0)
299 #define SMC_ECC_CTRL_SWRST BV(1)
303 * Defines for bit fields in SMC_ECC_MD register
306 #define SMC_ECC_MD_ECC_PAGESIZE_SHIFT 0
307 #define SMC_ECC_MD_ECC_PAGESIZE_MASK 0x3
308 #define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 0x0
309 #define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 0x1
310 #define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 0x2
311 #define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 0x3
312 #define SMC_ECC_MD_TYPCORREC_SHIFT 4
313 #define SMC_ECC_MD_TYPCORREC_MASK (0x3 << SMC_ECC_MD_TYPCORREC_SHIFT)
314 #define SMC_ECC_MD_TYPCORREC_CPAGE (0x0 << SMC_ECC_MD_TYPCORREC_SHIFT)
315 #define SMC_ECC_MD_TYPCORREC_C256B (0x1 << SMC_ECC_MD_TYPCORREC_SHIFT)
316 #define SMC_ECC_MD_TYPCORREC_C512B (0x2 << SMC_ECC_MD_TYPCORREC_SHIFT)
320 * Defines for bit fields in SMC_SETUP registers.
323 #define SMC_SETUP_NWE_SETUP_MASK 0x3f
324 #define SMC_SETUP_NWE_SETUP(x) (SMC_SETUP_NWE_SETUP_MASK & (x))
325 #define SMC_SETUP_NCS_WR_SETUP_SHIFT 8
326 #define SMC_SETUP_NCS_WR_SETUP_MASK (0x3f << SMC_SETUP_NCS_WR_SETUP_SHIFT)
327 #define SMC_SETUP_NCS_WR_SETUP(x) (SMC_SETUP_NCS_WR_SETUP_MASK & ((x) << SMC_SETUP_NCS_WR_SETUP_SHIFT))
328 #define SMC_SETUP_NRD_SETUP_SHIFT 16
329 #define SMC_SETUP_NRD_SETUP_MASK (0x3f << SMC_SETUP_NRD_SETUP_SHIFT)
330 #define SMC_SETUP_NRD_SETUP(x) (SMC_SETUP_NRD_SETUP_MASK & ((x) << SMC_SETUP_NRD_SETUP_SHIFT))
331 #define SMC_SETUP_NCS_RD_SETUP_SHIFT 24
332 #define SMC_SETUP_NCS_RD_SETUP_MASK (0x3f << SMC_SETUP_NCS_RD_SETUP_SHIFT)
333 #define SMC_SETUP_NCS_RD_SETUP(x) (SMC_SETUP_NCS_RD_SETUP_MASK & ((x) << SMC_SETUP_NCS_RD_SETUP_SHIFT))
337 * Defines for bit fields in SMC_PULSE registers.
340 #define SMC_PULSE_NWE_PULSE_MASK 0x3f
341 #define SMC_PULSE_NWE_PULSE(x) (SMC_PULSE_NWE_PULSE_MASK & (x))
342 #define SMC_PULSE_NCS_WR_PULSE_SHIFT 8
343 #define SMC_PULSE_NCS_WR_PULSE_MASK (0x3f << SMC_PULSE_NCS_WR_PULSE_SHIFT)
344 #define SMC_PULSE_NCS_WR_PULSE(x) (SMC_PULSE_NCS_WR_PULSE_MASK & ((x) << SMC_PULSE_NCS_WR_PULSE_SHIFT))
345 #define SMC_PULSE_NRD_PULSE_SHIFT 16
346 #define SMC_PULSE_NRD_PULSE_MASK (0x3f << SMC_PULSE_NRD_PULSE_SHIFT)
347 #define SMC_PULSE_NRD_PULSE(x) (SMC_PULSE_NRD_PULSE_MASK & ((x) << SMC_PULSE_NRD_PULSE_SHIFT))
348 #define SMC_PULSE_NCS_RD_PULSE_SHIFT 24
349 #define SMC_PULSE_NCS_RD_PULSE_MASK (0x3f << SMC_PULSE_NCS_RD_PULSE_SHIFT)
350 #define SMC_PULSE_NCS_RD_PULSE(x) (SMC_PULSE_NCS_RD_PULSE_MASK & ((x) << SMC_PULSE_NCS_RD_PULSE_SHIFT))
354 * Defines for bit fields in SMC_CYCLE registers.
357 #define SMC_CYCLE_NWE_CYCLE_MASK 0x1ff
358 #define SMC_CYCLE_NWE_CYCLE(x) (SMC_CYCLE_NWE_CYCLE_MASK & (x))
359 #define SMC_CYCLE_NRD_CYCLE_SHIFT 16
360 #define SMC_CYCLE_NRD_CYCLE_MASK (0x1ff << SMC_CYCLE_NRD_CYCLE_SHIFT)
361 #define SMC_CYCLE_NRD_CYCLE(x) (SMC_CYCLE_NRD_CYCLE_MASK & ((x) << SMC_CYCLE_NRD_CYCLE_SHIFT))
365 * Defines for bit fields in SMC_TIMINGS registers.
368 #define SMC_TIMINGS_TCLR_SHIFT 0
369 #define SMC_TIMINGS_TCLR_MASK (0xf << SMC_TIMINGS_TCLR_SHIFT)
370 #define SMC_TIMINGS_TCLR(value) (SMC_TIMINGS_TCLR_MASK & ((value) << SMC_TIMINGS_TCLR_SHIFT))
371 #define SMC_TIMINGS_TADL_SHIFT 4
372 #define SMC_TIMINGS_TADL_MASK (0xf << SMC_TIMINGS_TADL_SHIFT)
373 #define SMC_TIMINGS_TADL(value) (SMC_TIMINGS_TADL_MASK & ((value) << SMC_TIMINGS_TADL_SHIFT))
374 #define SMC_TIMINGS_TAR_SHIFT 8
375 #define SMC_TIMINGS_TAR_MASK (0xf << SMC_TIMINGS_TAR_SHIFT)
376 #define SMC_TIMINGS_TAR(value) (SMC_TIMINGS_TAR_MASK & ((value) << SMC_TIMINGS_TAR_SHIFT))
377 #define SMC_TIMINGS_OCMS BV(12)
378 #define SMC_TIMINGS_TRR_SHIFT 16
379 #define SMC_TIMINGS_TRR_MASK (0xf << SMC_TIMINGS_TRR_SHIFT)
380 #define SMC_TIMINGS_TRR(value) (SMC_TIMINGS_TRR_MASK & ((value) << SMC_TIMINGS_TRR_SHIFT))
381 #define SMC_TIMINGS_TWB_SHIFT 24
382 #define SMC_TIMINGS_TWB_MASK (0xf << SMC_TIMINGS_TWB_SHIFT)
383 #define SMC_TIMINGS_TWB(value) (SMC_TIMINGS_TWB_MASK & ((value) << SMC_TIMINGS_TWB_SHIFT))
384 #define SMC_TIMINGS_RBNSEL_SHIFT 28
385 #define SMC_TIMINGS_RBNSEL_MASK (0x7 << SMC_TIMINGS_RBNSEL_SHIFT)
386 #define SMC_TIMINGS_RBNSEL(value) (SMC_TIMINGS_RBNSEL_MASK & ((value) << SMC_TIMINGS_RBNSEL_SHIFT))
387 #define SMC_TIMINGS_NFSEL BV(31)
391 * Defines for bit fields in SMC_MODE registers.
394 #define SMC_MODE_READ_MODE BV(0)
395 #define SMC_MODE_WRITE_MODE BV(1)
396 #define SMC_MODE_EXNW_MODE_SHIFT 4
397 #define SMC_MODE_EXNW_MODE_MASK (0x3 << SMC_MODE_EXNW_MODE_SHIFT)
398 #define SMC_MODE_EXNW_MODE_DISABLED (0x0 << SNC_MODE_EXNW_MODE_SHIFT)
399 #define SMC_MODE_EXNW_MODE_FROZEN (0x2 << SNC_MODE_EXNW_MODE_SHIFT)
400 #define SMC_MODE_EXNW_MODE_READY (0x3 << SNC_MODE_EXNW_MODE_SHIFT)
401 #define SMC_MODE_BAT BV(8)
402 #define SMC_MODE_DBW BV(12)
403 #define SMC_MODE_TDF_CYCLES_SHIFT 16
404 #define SMC_MODE_TDF_CYCLES_MASK (0xf << SMC_MODE_TDF_CYCLES_SHIFT)
405 #define SMC_MODE_TDF_CYCLES(x) (SMC_MODE_TDF_CYCLES_MASK & ((x) << SMC_MODE_TDF_CYCLES_SHIFT))
406 #define SMC_MODE_TDF_MODE BV(20)
409 #endif /* CPU_CM3_SAM3X || CPU_CM3_SAM3U */
411 #endif /* SAM3_SMC_H */