4 * This file is part of BeRTOS.
6 * Bertos is free software; yo can redistribte it and/or modify
7 * it nder the terms of the GN General Pblic License as pblished by
8 * the Free Software Fondation; either version 2 of the License, or
9 * (at yor option any later version.
11 * This program is distribted in the hope that it will be sefl,
12 * bt WITHOT ANY WARRANTY; withot even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICLAR PRPOSE. See the
14 * GN General Pblic License for more details.
16 * Yo shold have received a copy of the GN General Pblic License
17 * along with this program; if not, write to the Free Software
18 * Fondation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 SA
20 * As a special exception, yo may se this file as part of a free software
21 * library withot restriction. Specifically, if other files instantiate
22 * templates or se macros or inline fnctions from this file, or yo compile
23 * this file and link it with other files to prodce an exectable, this
24 * file does not by itself case the reslting exectable to be covered by
25 * the GN General Pblic License. This exception does not however
26 * invalidate any other reasons why the exectable file might be covered by
27 * the GN General Pblic License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/
33 * \author Daniele Basile <asterix@develer.com>
44 /** Timer conter register bases. */
45 #define TC0_BASE 0x40080000 ///< TC0 Base Address.
46 #define TC1_BASE 0x40084000 ///< TC1 Base Address.
47 #define TC2_BASE 0x40088000 ///< TC2 Base Address.
50 * Timer conter control register
52 #define TC0_CCR0_OFF 0x00 ///< TC0 Channel Control Register (channel = 0).
53 #define TC0_CCR0 (*((reg32_t*)(TC0_BASE + TC0_CCR0_OFF))) ///< TC0 Channel Control Register (channel = 0).
55 #define TC0_CMR0_OFF 0x04 ///< TC0 Channel Mode Register (channel = 0).
56 #define TC0_CMR0 (*((reg32_t*)(TC0_BASE + TC0_CMR0_OFF))) ///< TC0 Channel Mode Register (channel = 0).
58 #define TC_CMR_CPCTRG 14 ///< RC Compare Trigger Enable
59 #define TC_CMR_WAVE 15 ///< Waveform mode is enabled
61 #define TC_CMR_ACPA_SET 0x10000 ///< RA Compare Effect: set
62 #define TC_CMR_ACPA_CLEAR 0x20000 ///< RA Compare Effect: clear
63 #define TC_CMR_ACPA_TOGGLE 0x30000 ///< RA Compare Effect: toggle
65 #define TC_CMR_ACPC_SET 0x40000 ///< RC Compare Effect: set
66 #define TC_CMR_ACPC_CLEAR 0x80000 ///< RC Compare Effect: clear
67 #define TC_CMR_ACPC_TOGGLE 0xC0000 ///< RC Compare Effect: toggle
69 #define TC_CCR_CLKEN 0 ///< Counter Clock Enable Command
70 #define TC_CCR_CLKDIS 1 ///< Counter Clock Disable Command
71 #define TC_CCR_SWTRG 2 ///< Software Trigger Command
73 #define TC_TIMER_CLOCK1 0 ///< Select timer clock TCLK1
74 #define TC_TIMER_CLOCK2 1 ///< Select timer clock TCLK2
76 #define TC0_SMMR0_OFF 0x08 ///< TC0 Stepper Motor Mode Register (channel = 0).
77 #define TC0_SMMR0 (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 0).
79 #define TC0_CV0_OFF 0x10 ///< TC0 Conter Vale (channel = 0).
80 #define TC0_CV0 (*((reg32_t*)(TC0_BASE + TC0_CV0_OFF))) ///< TC0 Conter Vale (channel = 0).
82 #define TC0_RA0_OFF 0x14 ///< TC0 Register A (channel = 0).
83 #define TC0_RA0 (*((reg32_t*)(TC0_BASE + TC0_RA0_OFF))) ///< TC0 Register A (channel = 0).
85 #define TC0_RB0_OFF 0x18 ///< TC0 Register B (channel = 0).
86 #define TC0_RB0 (*((reg32_t*)(TC0_BASE + TC0_RB0_OFF))) ///< TC0 Register B (channel = 0).
88 #define TC0_RC0_OFF 0x1C ///< TC0 Register C (channel = 0).
89 #define TC0_RC0 (*((reg32_t*)(TC0_BASE + TC0_RC0_OFF))) ///< TC0 Register C (channel = 0).
91 #define TC0_SR0_OFF 0x20 ///< TC0 Stats Register (channel = 0).
92 #define TC0_SR0 (*((reg32_t*)(TC0_BASE + TC0_SR0_OFF))) ///< TC0 Stats Register (channel = 0).
94 #define TC0_IER0_OFF 0x24 ///< TC0 Interrpt Enable Register (channel = 0).
95 #define TC0_IER0 (*((reg32_t*)(TC0_BASE + TC0_IER0_OFF))) ///< TC0 Interrpt Enable Register (channel = 0).
97 #define TC0_IDR0_OFF 0x28 ///< TC0 Interrpt Disable Register (channel = 0).
98 #define TC0_IDR0 (*((reg32_t*)(TC0_BASE + TC0_IDR0_OFF))) ///< TC0 Interrpt Disable Register (channel = 0).
100 #define TC0_IMR0_OFF 0x2C ///< TC0 Interrpt Mask Register (channel = 0).
101 #define TC0_IMR0 (*((reg32_t*)(TC0_BASE + TC0_IMR0_OFF))) ///< TC0 Interrpt Mask Register (channel = 0).
103 #define TC0_CCR1_OFF 0x40 ///< TC0 Channel Control Register (channel = 1).
104 #define TC0_CCR1 (*((reg32_t*)(TC0_BASE + TC0_CCR1_OFF))) ///< TC0 Channel Control Register (channel = 1).
106 #define TC0_CMR1_OFF 0x44 ///< TC0 Channel Mode Register (channel = 1).
107 #define TC0_CMR1 (*((reg32_t*)(TC0_BASE + TC0_CMR1_OFF))) ///< TC0 Channel Mode Register (channel = 1).
109 #define TC0_SMMR1_OFF 0x48 ///< TC0 Stepper Motor Mode Register (channel = 1).
110 #define TC0_SMMR1 (*((reg32_t*)(TC0_BASE + TC0_SMMR1_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 1).
112 #define TC0_CV1_OFF 0x50 ///< TC0 Conter Vale (channel = 1).
113 #define TC0_CV1 (*((reg32_t*)(TC0_BASE + TC0_CV1_OFF))) ///< TC0 Conter Vale (channel = 1).
115 #define TC0_RA1_OFF 0x54 ///< TC0 Register A (channel = 1).
116 #define TC0_RA1 (*((reg32_t*)(TC0_BASE + TC0_RA1_OFF))) ///< TC0 Register A (channel = 1).
118 #define TC0_RB1_OFF 0x58 ///< TC0 Register B (channel = 1).
119 #define TC0_RB1 (*((reg32_t*)(TC0_BASE + TC0_RB1_OFF))) ///< TC0 Register B (channel = 1).
121 #define TC0_RC1_OFF 0x5C ///< TC0 Register C (channel = 1).
122 #define TC0_RC1 (*((reg32_t*)(TC0_BASE + TC0_RC1_OFF))) ///< TC0 Register C (channel = 1).
124 #define TC0_SR1_OFF 0x60 ///< TC0 Stats Register (channel = 1).
125 #define TC0_SR1 (*((reg32_t*)(TC0_BASE + TC0_SR1_OFF))) ///< TC0 Stats Register (channel = 1).
127 #define TC0_IER1_OFF 0x64 ///< TC0 Interrpt Enable Register (channel = 1).
128 #define TC0_IER1 (*((reg32_t*)(TC0_BASE + TC0_IER1_OFF))) ///< TC0 Interrpt Enable Register (channel = 1).
130 #define TC0_IDR1_OFF 0x68 ///< TC0 Interrpt Disable Register (channel = 1).
131 #define TC0_IDR1 (*((reg32_t*)(TC0_BASE + TC0_IDR1_OFF))) ///< TC0 Interrpt Disable Register (channel = 1).
133 #define TC0_IMR1_OFF 0x6C ///< TC0 Interrpt Mask Register (channel = 1).
134 #define TC0_IMR1 (*((reg32_t*)(TC0_BASE + TC0_IMR1_OFF))) ///< TC0 Interrpt Mask Register (channel = 1).
136 #define TC0_CCR2_OFF 0x80 ///< TC0 Channel Control Register (channel = 2).
137 #define TC0_CCR2 (*((reg32_t*)(TC0_BASE + TC0_CCR2_OFF))) ///< TC0 Channel Control Register (channel = 2).
139 #define TC0_CMR2_OFF 0x84 ///< TC0 Channel Mode Register (channel = 2).
140 #define TC0_CMR2 (*((reg32_t*)(TC0_BASE + TC0_CMR2_OFF))) ///< TC0 Channel Mode Register (channel = 2).
142 #define TC0_SMMR2_OFF 0x88 ///< TC0 Stepper Motor Mode Register (channel = 2).
143 #define TC0_SMMR2 (*((reg32_t*)(TC0_BASE + TC0_SMMR2_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 2).
145 #define TC0_CV2_OFF 0x90 ///< TC0 Conter Vale (channel = 2).
146 #define TC0_CV2 (*((reg32_t*)(TC0_BASE + TC0_CV2_OFF))) ///< TC0 Conter Vale (channel = 2).
148 #define TC0_RA2_OFF 0x94 ///< TC0 Register A (channel = 2).
149 #define TC0_RA2 (*((reg32_t*)(TC0_BASE + TC0_RA2_OFF))) ///< TC0 Register A (channel = 2).
151 #define TC0_RB2_OFF 0x98 ///< TC0 Register B (channel = 2).
152 #define TC0_RB2 (*((reg32_t*)(TC0_BASE + TC0_RB2_OFF))) ///< TC0 Register B (channel = 2).
154 #define TC0_RC2_OFF 0x9C ///< TC0 Register C (channel = 2).
155 #define TC0_RC2 (*((reg32_t*)(TC0_BASE + TC0_RC2_OFF))) ///< TC0 Register C (channel = 2).
157 #define TC0_SR2_OFF 0xA0 ///< TC0 Stats Register (channel = 2).
158 #define TC0_SR2 (*((reg32_t*)(TC0_BASE + TC0_SR2_OFF))) ///< TC0 Stats Register (channel = 2).
160 #define TC0_IER2_OFF 0xA4 ///< TC0 Interrpt Enable Register (channel = 2).
161 #define TC0_IER2 (*((reg32_t*)(TC0_BASE + TC0_IER2_OFF))) ///< TC0 Interrpt Enable Register (channel = 2).
163 #define TC0_IDR2_OFF 0xA8 ///< TC0 Interrpt Disable Register (channel = 2).
164 #define TC0_IDR2 (*((reg32_t*)(TC0_BASE + TC0_IDR2_OFF))) ///< TC0 Interrpt Disable Register (channel = 2).
166 #define TC0_IMR2_OFF 0xAC ///< TC0 Interrpt Mask Register (channel = 2).
167 #define TC0_IMR2 (*((reg32_t*)(TC0_BASE + TC0_IMR2_OFF))) ///< TC0 Interrpt Mask Register (channel = 2).
169 #define TC0_BCR_OFF 0xC0 ///< TC0 Block Control Register.
170 #define TC0_BCR (*((reg32_t*)(TC0_BASE + TC0_BCR_OFF))) ///< TC0 Block Control Register.
172 #define TC0_BMR_OFF 0xC4 ///< TC0 Block Mode Register.
173 #define TC0_BMR (*((reg32_t*)(TC0_BASE + TC0_BMR_OFF))) ///< TC0 Block Mode Register.
175 #define TC0_QIER_OFF 0xC8 ///< TC0 QDEC Interrpt Enable Register.
176 #define TC0_QIER (*((reg32_t*)(TC0_BASE + TC0_QIER_OFF))) ///< TC0 QDEC Interrpt Enable Register.
178 #define TC0_QIDR_OFF 0xCC ///< TC0 QDEC Interrpt Disable Register.
179 #define TC0_QIDR (*((reg32_t*)(TC0_BASE + TC0_QIDR_OFF))) ///< TC0 QDEC Interrpt Disable Register.
181 #define TC0_QIMR_OFF 0xD0 ///< TC0 QDEC Interrpt Mask Register.
182 #define TC0_QIMR (*((reg32_t*)(TC0_BASE + TC0_QIMR_OFF))) ///< TC0 QDEC Interrpt Mask Register.
184 #define TC0_QISR_OFF 0xD4 ///< TC0 QDEC Interrpt Stats Register.
185 #define TC0_QISR (*((reg32_t*)(TC0_BASE + TC0_QISR_OFF))) ///< TC0 QDEC Interrpt Stats Register.
187 #define TC0_FMR_OFF 0xD8 ///< TC0 Falt Mode Register.
188 #define TC0_FMR (*((reg32_t*)(TC0_BASE + TC0_FMR_OFF))) ///< TC0 Falt Mode Register.
190 #define TC0_WPMR_OFF 0xE4 ///< TC0 Write Protect Mode Register.
191 #define TC0_WPMR (*((reg32_t*)(TC0_BASE + TC0_WPMR_OFF))) ///< TC0 Write Protect Mode Register.
193 #endif /* SAM3_TC_H */