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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Cortex-M3 IRQ management.
35 * \author Andrea Righi <arighi@develer.com>
40 #include <cfg/debug.h> /* ASSERT() */
41 #include <cfg/log.h> /* LOG_ERR() */
45 #ifdef __IAR_SYSTEMS_ICC__
46 #pragma data_alignment=0x400
47 static void (*irq_table[NUM_INTERRUPTS])(void);
49 static void (*irq_table[NUM_INTERRUPTS])(void)
50 __attribute__((section("vtable")));
53 /* Priority register / IRQ number table */
54 static const uint32_t nvic_prio_reg[] =
56 /* System exception registers */
57 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3,
59 /* External interrupts registers */
60 NVIC_PRI0, NVIC_PRI1, NVIC_PRI2, NVIC_PRI3,
61 NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
62 NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11,
63 NVIC_PRI12, NVIC_PRI13
67 static NAKED NORETURN void unhandled_isr(void)
69 register uint32_t reg;
71 #ifdef __IAR_SYSTEMS_ICC__
72 reg = CPU_READ_IPSR();
74 asm volatile ("mrs %0, ipsr" : "=r"(reg));
76 LOG_ERR("unhandled IRQ %lu\n", reg);
81 void sysirq_setPriority(sysirq_t irq, int prio)
83 uint32_t pos = (irq & 3) * 8;
84 reg32_t reg = nvic_prio_reg[irq >> 2];
88 val &= ~(0xff << pos);
93 static void sysirq_enable(sysirq_t irq)
95 /* Enable the IRQ line (only for generic IRQs) */
96 if (irq >= 16 && irq < 48)
97 NVIC_EN0_R = 1 << (irq - 16);
99 NVIC_EN1_R = 1 << (irq - 48);
102 void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
106 ASSERT(irq < NUM_INTERRUPTS);
108 IRQ_SAVE_DISABLE(flags);
109 irq_table[irq] = handler;
110 sysirq_setPriority(irq, IRQ_PRIO);
115 void sysirq_freeHandler(sysirq_t irq)
119 ASSERT(irq < NUM_INTERRUPTS);
121 IRQ_SAVE_DISABLE(flags);
122 irq_table[irq] = unhandled_isr;
126 void sysirq_init(void)
131 IRQ_SAVE_DISABLE(flags);
132 for (i = 0; i < NUM_INTERRUPTS; i++)
133 irq_table[i] = unhandled_isr;
135 /* Update NVIC to point to the new vector table */
136 NVIC_VTABLE_R = (size_t)irq_table;